SST25VF010-20-4C-SAE Microchip Technology, SST25VF010-20-4C-SAE Datasheet - Page 5
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
SST25VF010-20-4C-SAE
Manufacturer Part Number
SST25VF010-20-4C-SAE
Description
Flash 128K X 8 14 s
Manufacturer
Microchip Technology
Datasheet
1.SST25VF010-20-4C-QAE.pdf
(22 pages)
Specifications of SST25VF010-20-4C-SAE
Product Category
Flash
Rohs
yes
Memory Type
NAND Flash
Memory Size
1 Mbit
Architecture
Sectored
Interface Type
SPI
Access Time
20 ns
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
Maximum Operating Current
10 mA
Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
SOIC-8
Organization
32 KB
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SST25VF010-20-4C-SAE
Manufacturer:
SST
Quantity:
20 000
Company:
Part Number:
SST25VF010-20-4C-SAE-CT010
Manufacturer:
RENESAS
Quantity:
3 250
Company:
Part Number:
SST25VF010-20-4C-SAE-CT010
Manufacturer:
SST
Quantity:
8 000
Part Number:
SST25VF010-20-4C-SAE-T
Manufacturer:
SST
Quantity:
20 000
1 Mbit SPI Serial Flash
SST25VF010
Hold Operation
HOLD# pin is used to pause a serial sequence underway
with the SPI flash memory without resetting the clocking
sequence. To activate the HOLD# mode, CE# must be in
active low state. The HOLD# mode begins when the SCK
active low state coincides with the falling edge of the
HOLD# signal. The HOLD mode ends when the HOLD#
signal’s rising edge coincides with the SCK active low state.
If the falling edge of the HOLD# signal does not coincide
with the SCK active low state, then the device enters Hold
mode when the SCK next reaches the active low state.
Similarly, if the rising edge of the HOLD# signal does not
Write Protection
The SST25VF010 provides software Write protection. The
Write Protect pin (WP#) enables or disables the lock-down
function of the status register. The Block-Protection bits
(BP1, BP0, and BPL) in the status register provide Write
protection to the memory array and the status register. See
Table 4 for Block-Protection description.
Write Protect Pin (WP#)
The Write Protect (WP#) pin enables the lock-down func-
tion of the BPL bit (bit 7) in the status register. When WP#
is driven low, the execution of the Write-Status-Register
(WRSR) instruction is determined by the value of the BPL
bit (see Table 3). When WP# is high, the lock-down func-
tion of the BPL bit is disabled.
©2006 Silicon Storage Technology, Inc.
HOLD#
FIGURE 3: H
SCK
OLD
Active
C
ONDITION
W
AVEFORM
Hold
5
coincide with the SCK active low state, then the device
exits in Hold mode when the SCK next reaches the active
low state. See Figure 3 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-
impedance state while SI and SCK can be V
If CE# is driven active high during a Hold condition, it resets
the internal logic of the device. As long as HOLD# signal is
low, the memory remains in the Hold condition. To resume
communication with the device, HOLD# must be driven
active high, and CE# must be driven active low. See Figure
17 for Hold timing.
TABLE 3: C
WP#
H
L
L
Active
R
ONDITIONS TO EXECUTE
EGISTER
BPL
X
1
0
Hold
(WRSR) I
Execute WRSR Instruction
Not Allowed
Allowed
Allowed
NSTRUCTION
S71233-05-000
Active
W
RITE
IL
Data Sheet
or V
-S
1233 F03.0
TATUS
IH
T3.0 1233
.
1/06
-