GLS85LP1008B-M-C-LFTE (rev. CB1) Greenliant, GLS85LP1008B-M-C-LFTE (rev. CB1) Datasheet - Page 8

• Manufacturer Part Number: GLS85LP1008B-M-C-LFTE (rev. CB1)
• Description: Flash 8G MLC, NAND MLC 3.3V Comm
• Manufacturer: Greenliant

Specifications of GLS85LP1008B-M-C-LFTE (rev. CB1)

• Product Category: Flash
• Rohs: yes

Advance Information
©2010 Greenliant Systems, Ltd.
Symbol
IORDY
IOCS16#
INTRQ
PDIAG#
DASP#
RESET#
Serial Communication Interface (SCI)
SCID
SCID
SCICLK
Miscellaneous
WP#/PD#
V
V
DNU
SS
DD
1. Any VSS or V
1
1
Table 1: Pin Assignments (Continued) (2 of 2)
OUT
IN
K4, K6, K7, J9
E5,E6, F5, G5,
J7, L4, L6, L7,
R2, R9, R10,
A10, B1, B9,
M3, M4, M5,
M6, M7, M8,
B10,D2, D3,
G4, G6, G7,
E2, E9, K5,
L5, M2, M9
D4, D5, D6,
N2, N3, N4,
N5, N6, N7,
N8, N9, R1,
A1, A2, A9,
T1, T2, T9,
91-LBGA
Pin No.
T10
K9
D9
E4
D8
D7
E7
J4
J8
J2
F6
DD
pin must not be left open or floating.
Type
PWR
PWR
Pin
I/O
I/O
O
O
O
O
I
I
I
I
I1U/O2 The Pass Diagnostic signal in the Master/Slave handshake protocol.
I1U/O4 The Drive Active/Slave Present signal in the Master/Slave handshake
Type Name and Functions
I2U
I1U
I1D
I2U
I/O
O2
O3
O2
O2
IORDY: When in PIO mode, the device is not ready to respond to a data
transfer request. This signal is negated to extend the Host transfer
cycle from the assertion of IORD# or IOWR#. However, it is never
negated by this controller. (This pin supports three functions)
DDMARDY#: When Ultra DMA mode DMA Write is active, this signal is
asserted by the device to indicate that the device is ready to receive
Ultra DMA data-out bursts. The device may negate DDMARDY# to
pause an Ultra DMA transfer.
DSTROBE: When Ultra DMA mode DMA Read is active, this signal is
the data-in strobe generated by the device. Both the rising and falling
edges of DSTROBE cause data to be latched by the host. The device
may stop generating DSTROBE edges to pause an Ultra DMA data-in
burst.
This output signal is asserted low when the device is indicating a word
data transfer cycle.
This signal is the active high Interrupt Request to the host.
protocol.
This input pin is the active low hardware reset from the host.
SCI interface data output
SCI interface data input
SCI interface clock
The WP#/PD# pin can be used for either the Write Protect mode or Power-down
mode, but only one mode is active at any time. The Write Protect or Power-down
modes can be selected through the host command. The Write Protect mode is
the factory default setting.
Ground
V
Do not use.
DD
(3.3V)
8
8 GByte NANDrive
GLS85LP1008B
S71421-02-000
T1.4 1421
05/10