PCAL9555APW,118 NXP Semiconductors, PCAL9555APW,118 Datasheet - Page 11

• Manufacturer Part Number: PCAL9555APW,118
• Description: Interface - I/O Expanders 16b I2C BUS INTERUPT
• Manufacturer: NXP Semiconductors

Specifications of PCAL9555APW,118

• Rohs: yes
• Maximum Operating Frequency: 100 kHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-24
• Operating Current: 160 mA
• Output Current: 25 mA
• Power Dissipation: 200 mW
• Product Type: I/O Expanders
• Factory Pack Quantity: 2500

NXP Semiconductors
PCAL9555A
Product data sheet
6.2.10 Interrupt mask register pair (4Ah, 4Bh)
6.2.9 Pull-up/pull-down selection register pair (48h, 49h)
The I/O port can be configured to have a pull-up or pull-down resistor by programming the
pull-up/pull-down selection register. Setting a bit to logic 1 selects a 100 k pull-up
resistor for that I/O pin. Setting a bit to logic 0 selects a 100 k pull-down resistor for that
I/O pin. If the pull-up/pull-down feature is disconnected, writing to this register will have no
effect on I/O pin. Typical value is 100 k with minimum of 50 k and maximum of 150 k.
A register pair write is described in
Section
Table 21.
Table 22.
Interrupt mask registers are set to logic 1 upon power-on, disabling interrupts during
system start-up. Interrupts may be enabled by setting corresponding mask bits to logic 0.
If an input changes state and the corresponding bit in the Interrupt mask register is set
to 1, the interrupt is masked and the interrupt pin will not be asserted. If the corresponding
bit in the Interrupt mask register is set to 0, the interrupt pin will be asserted.
When an input changes state and the resulting interrupt is masked (interrupt mask bit
is 1), setting the input mask register bit to 0 will cause the interrupt pin to be asserted.
If the interrupt mask bit of an input that is currently the source of an interrupt is set to 1,
the interrupt pin will be de-asserted. A register pair write is described in
register pair read is described in
Table 23.
Table 24.
Bit
Symbol
Default
Bit
Symbol
Default
Bit
Symbol
Default
Bit
Symbol
Default
7.2.
Pull-up/pull-down selection port 0 register (address 48h)
Pull-up/pull-down selection port 1 register (address 49h)
Interrupt mask port 0 register (address 4Ah) bit description
Interrupt mask port 1 register (address 4Bh) bit description
PUD0.7
PUD1.7
M0.7
M1.7
7
1
7
1
7
1
7
1
All information provided in this document is subject to legal disclaimers.
Low-voltage 16-bit GPIO with Agile I/O, interrupt and weak pull-up
PUD0.6
PUD1.6
M0.6
M1.6
Rev. 1 — 3 October 2012
6
1
6
1
6
1
6
1
PUD0.5
PUD1.5
M0.5
M1.5
Section
5
1
5
1
5
1
5
1
Section 7.1
PUD0.4
PUD1.4
7.2.
M0.4
M1.4
4
1
4
1
4
1
4
1
and a register pair read is described in
PUD0.3
PUD1.3
M0.3
M1.3
3
1
3
1
3
1
3
1
PUD0.2
PUD1.2
M0.2
M1.2
PCAL9555A
2
1
2
1
2
1
2
1
PUD0.1
PUD1.1
© NXP B.V. 2012. All rights reserved.
Section 7.1
M0.1
M1.1
1
1
1
1
1
1
1
1
PUD0.0
PUD1.0
M0.0
M1.0
11 of 46
and a
0
1
0
1
0
1
0
1