PCAL9555APW,118 NXP Semiconductors, PCAL9555APW,118 Datasheet - Page 23

• Manufacturer Part Number: PCAL9555APW,118
• Description: Interface - I/O Expanders 16b I2C BUS INTERUPT
• Manufacturer: NXP Semiconductors

Specifications of PCAL9555APW,118

• Rohs: yes
• Maximum Operating Frequency: 100 kHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-24
• Operating Current: 160 mA
• Output Current: 25 mA
• Power Dissipation: 200 mW
• Product Type: I/O Expanders
• Factory Pack Quantity: 2500

NXP Semiconductors
Table 28.
T
[1]
[2]
PCAL9555A
Product data sheet
Symbol
(dV/dt)
(dV/dt)
t
V
t
V
d(rst)
w(gl)VDD
amb
POR(trip)
DD(gl)
Level that V
Glitch width that will not cause a functional disruption when V
= 25
f
r

C (unless otherwise noted). Not tested; specified by design.
Recommended supply sequencing and ramp rates
Parameter
fall rate of change of voltage
rise rate of change of voltage
reset delay time
glitch supply voltage difference
supply voltage glitch pulse width
power-on reset trip voltage
DD
can glitch down to with a ramp rate of 0.4 s/V, but not cause a functional disruption when t
Glitches in the power supply can also affect the power-on reset performance of this
device. The glitch width (t
other. The bypass capacitance, source impedance, and device impedance are factors that
affect power-on reset performance.
how to measure these specifications.
V
is released and all the registers and the I
their default states. The value of V
0 V.
Fig 19. Glitch width and glitch height
Fig 20. Power-on reset voltage (V
POR
V
V
POR
POR
Figure 20
is critical to the power-on reset. V
(falling V
(rising V
V
DD
DD
DD
∆V
)
)
and
POR
V
DD(gl)
All information provided in this document is subject to legal disclaimers.
DD
Low-voltage 16-bit GPIO with Agile I/O, interrupt and weak pull-up
Table 28
Condition
Figure 17
Figure 17
Figure
V
Figure
V
Figure 19
Figure 19
falling V
rising V
Rev. 1 — 3 October 2012
DD
DD
w(gl)VDD
drops below 0.2 V or to V
drops to V
17; re-ramp time when
18; re-ramp time when
provide more details on this specification.
DD
DD
t
DD(gl)
w(gl)VDD
) and glitch height (V
POR
POR
POR(min)
= 0.5  V
Figure 19
)
POR
differs based on the V
2
C-bus/SMBus state machine are initialized to
 50 mV
is the voltage level at which the reset condition
DD
.
and
SS
Table 28
[1]
[2]
DD(gl)
Min
0.1
0.1
1
1
-
-
0.7
-
provide more information on
) are dependent on each
DD
being lowered to or from
PCAL9555A
Typ
-
-
-
-
-
-
-
-
w(gl)VDD
© NXP B.V. 2012. All rights reserved.
< 1 s.
Max
2000
2000
-
-
1
10
-
1.4
002aah331
time
002aah332
Unit
ms
ms
s
s
V
s
V
V
23 of 46
time
time