MAX9218ECM-T Maxim Integrated, MAX9218ECM-T Datasheet - Page 10

• Manufacturer Part Number: MAX9218ECM-T
• Description: Serializers & Deserializers - Serdes 27-Bit DC-Balanced Deserializer
• Manufacturer: Maxim Integrated
• Type: Deserializerr

Specifications of MAX9218ECM-T

• Data Rate: 700 Mbit/s
• Input Type: LVDS
• Output Type: LVCMOS/LVTTL
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-48
• Maximum Operating Temperature: + 85 C
• Maximum Power Dissipation: 1739 mW
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Current: 70 mA
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V

27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
The MAX9218 DC-balanced deserializer operates at a
parallel clock frequency of 3MHz to 35MHz, deserializ-
ing video data to the RGB_OUT[17:0] outputs when the
data enable output DE_OUT is high, or control data to
the CNTL_OUT[8:0] outputs when DE_OUT is low. The
video phase words are decoded using 2 overhead bits,
EN0 and EN1. Control phase words are decoded with 1
overhead bit, EN0. Encoding, performed by the
MAX9217 serializer, reduces EMI and maintains DC
balance across the serial cable. The serial input word
formats are shown in Table 1 and Table 2.
Control data inputs C0 to C4, each repeated over 3 seri-
al bit times by the serializer, are decoded using majority
voting. Two or three bits at the same state determine the
state of the recovered bit, providing single bit-error tol-
erance for C0 to C4. The state of C5 to C8 is deter-
mined by the level of the bit itself (no voting is used).
AC-coupling increases the input voltage of the LVDS
receiver to the voltage rating of the capacitor. Two
capacitors are sufficient for isolation, but four capaci-
tors—two at the serializer output and two at the deseri-
alizer input—provide protection if either end of the
cable is shorted to a high voltage. AC-coupling blocks
low-frequency ground shifts and common-mode noise.
The MAX9217 serializer can also be DC-coupled to the
MAX9218 deserializer. Figure 10 is the AC-coupled
serializer and deserializer with two capacitors per link,
and Figure 11 is the AC-coupled serializer and deseri-
alizer with four capacitors per link.
Table 1. Serial Video Phase Word Format
Bit 0 is the LSB and is deserialized first. EN[1:0] are encoding bits. S[17:0] are encoded symbols.
Table 2. Serial Control Phase Word Format
Bit 0 is the LSB and is deserialized first. C[8:0] are the mapped control inputs.
10
E N 0
EN0
0
0
______________________________________________________________________________________
EN1
C0
1
1
C0
S0
2
2
C0
S1
3
3
Detailed Description
C1
S2
4
4
AC-Coupling Benefits
C1
S3
5
5
C1
S4
6
6
C2
S5
7
7
C2
S6
8
8
C2
S7
9
9
S8
C3
10
10
See Figure 12 for calculating the capacitor values for
AC-coupling, depending on the parallel clock frequen-
cy. The plot shows capacitor values for two- and four-
capacitor-per-link systems. For applications using less
than 18MHz clock frequency, use 0.1µF capacitors.
The IN+ and IN- LVDS inputs are internally connected
to +1.2V through 35kΩ (min) to provide biasing for AC-
coupling (Figure 1). Assuming 100Ω interconnect, the
LVDS input can be terminated with a 100Ω resistor.
Match the termination to the differential impedance of
the interconnect.
Use a Thevenin termination, providing 1.2V bias, on an
AC-coupled link in noisy environments. For intercon-
nect with 100Ω differential impedance, pull each LVDS
line up to V
at the deserializer input (Figure 10 and Figure 11). This
termination provides both differential and common-
mode termination. The impedance of the Thevenin ter-
mination should be half the differential impedance of
the interconnect and provide a bias voltage of 1.2V.
C3
11
S9
11
Selection of AC-Coupling Capacitors
S10
C3
12
12
CC
with 130Ω and down to ground with 82Ω
Applications Information
S11
C4
13
13
Termination and Input Bias
S12
C4
14
14
S13
C4
15
15
S14
C5
16
16
S15
C6
17
17
S16
18
C7
18
S17
19
C8
19