MAX9218ECM-T Maxim Integrated, MAX9218ECM-T Datasheet - Page 12

• Manufacturer Part Number: MAX9218ECM-T
• Description: Serializers & Deserializers - Serdes 27-Bit DC-Balanced Deserializer
• Manufacturer: Maxim Integrated
• Type: Deserializerr

Specifications of MAX9218ECM-T

• Data Rate: 700 Mbit/s
• Input Type: LVDS
• Output Type: LVCMOS/LVTTL
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-48
• Maximum Operating Temperature: + 85 C
• Maximum Power Dissipation: 1739 mW
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Current: 70 mA
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V

27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
A frequency-detection circuit detects when the LVDS
input is not switching. When not switching, all outputs
except LOCK are low, LOCK is high, and PCLK_OUT
follows REFCLK. This condition occurs, for example, if
the serializer is not driving the interconnect or if the
interconnect is open.
The RNG[1:0] inputs select the operating frequency
range of the MAX9218 and the transition time of the out-
puts. Select the frequency range that includes the
MAX9217 serializer PCLK_IN frequency. Table 3 shows
the selectable frequency ranges and the corresponding
data rates and output transition times.
Driving PWRDWN low puts the outputs in high imped-
ance and stops the PLL. With PWRDWN ≤ 0.3V and all
LVTTL/LVCMOS inputs ≤ 0.3V or ≥ V
ply current is reduced to less than 50µA. Driving
PWRDWN high initiates lock to the local reference clock
(REFCLK) and afterwards to the serial input.
When PWRDWN is driven high, the PLL begins locking
to REFCLK, drives LOCK from high impedance to high
and the other outputs from high impedance to low
except PCLK_OUT. PCLK_OUT outputs REFCLK while
the PLL is locking to REFCLK. Locking to REFCLK
takes a maximum of 16,385 REFCLK cycles. When
locking to REFCLK is complete, the serial input is moni-
tored for a transition word. When a transition word is
found, LOCK is driven low indicating valid output data,
and the parallel rate clock recovered from the serial
input is output on PCLK_OUT. PCLK_OUT is stretched
on the change from REFCLK to recovered clock (or
vice versa).
Table 3. Frequency Range Programming
12
RNG1
0
0
1
1
______________________________________________________________________________________
Frequency Range Setting (RNG[1:0])
RNG0
0
1
0
1
PARALLEL
Lock and Loss of Lock ( LOCK )
15 to 35
CLOCK
7 to 15
(MHz)
3 to 7
Input Frequency Detection
DATA RATE
140 to 300
300 to 700
60 to 140
SERIAL
(Mbps)
CC
Power Down
- 0.3V, the sup-
TRANSITION
OUTPUT
TIME
Slow
Fast
If a transition word is not detected within 2
PCLK_OUT, LOCK is driven high and the other outputs
except PCLK_OUT are driven low. REFCLK is output on
PCLK_OUT and the deserializer continues monitoring
the serial input for a transition word. See Figure 7 for
the synchronization timing diagram.
The outputs of two MAX9218s can be bused to form a
2:1 mux with the outputs controlled by the output
enable. Wait 30ns between disabling one deserializer
(driving OUTEN low) and enabling the second one (dri-
ving OUTEN high) to avoid contention of the bused out-
puts. OUTEN controls all outputs.
The MAX9218 has a selectable rising or falling output
latch edge through a logic setting on R/F. Driving R/F
high selects the rising output latch edge, which latches
the parallel output data into the next chip on the rising
edge of PCLK_OUT. Driving R/F low selects the falling
output latch edge, which latches the parallel output
data into the next chip on the falling edge of
PCLK_OUT. The MAX9218 output-latch-edge polarity
does not need to match the MAX9217 serializer input-
latch-edge polarity. Select the latch-edge polarity
required by the chip being driven by the MAX9218.
Figure 12. AC-Coupling Capacitor Values vs. Clock Frequency
of 18MHz to 35MHz
Rising or Falling Output Latch Edge (R/ F )
140
125
110
95
80
65
50
35
20
18
vs. PARALLEL CLOCK FREQUENCY
AC-COUPLING CAPACITOR VALUE
PARALLEL CLOCK FREQUENCY (MHz)
21
Output Enable (OUTEN) and
TWO CAPACITORS PER LINK
FOUR CAPACITORS PER LINK
24
27
30
Busing Outputs
33
36
20
cycles of