MAX9218ECM-T Maxim Integrated, MAX9218ECM-T Datasheet - Page 4

• Manufacturer Part Number: MAX9218ECM-T
• Description: Serializers & Deserializers - Serdes 27-Bit DC-Balanced Deserializer
• Manufacturer: Maxim Integrated
• Type: Deserializerr

Specifications of MAX9218ECM-T

• Data Rate: 700 Mbit/s
• Input Type: LVDS
• Output Type: LVCMOS/LVTTL
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-48
• Maximum Operating Temperature: + 85 C
• Maximum Power Dissipation: 1739 mW
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Current: 70 mA
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V

27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
AC ELECTRICAL CHARACTERISTICS
(V
V
1.2V, T
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
Note 3: All LVTTL/LVCMOS inputs, except PWRDWN at ≤ 0.3V or ≥ V
Note 4: AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma.
Note 5: C
4
REFCLK TIMING REQUIREMENTS
Period
Frequency
Frequency Variation
Duty Cycle
Transition Time
SWITCHING CHARACTERISTICS
Output Rise Time
Output Fall Time
PCLK_OUT High Time
PCLK_OUT Low Time
Data Valid Before PCLK_OUT
Data Valid After PCLK_OUT
Input-to-Output Delay
PLL Lock to REFCLK
Power-Down Delay
Output Enable Time
Output Disable Time
CM
CC_
_______________________________________________________________________________________
= ⏐V
= +3.0V to 3.6V, C
A
= +25°C.) (Notes 4, 5)
except V
tested at T
ID
L
PARAMETER
/2⏐ to V
includes probe and test jig capacitance.
TH
CC
A
and V
= +25°C.
- ⏐V
ID
L
TL
/2⏐, T
= 8pF, PWRDWN = high, differential input voltage ⏐V
.
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
SYMBOL
t
t
PLLREF
Δf
t
t
DELAY
t
t
t
t
f
TRAN
HIGH
LOW
DC
DVB
DVA
PDD
t
t
CLK
t
OE
OZ
t
CLK
t
R
T
F
REFCLK to serializer PCLK_IN
20% to 80%
Figure 3
Figure 3
Figure 4
Figure 4
Figure 5
Figure 5
Figure 6
Figure 7
Figure 7
Figure 8
Figure 9
RNG1, RNG0 = high
RNG1, RNG0 both not high
simultaneously
RNG1, RNG0 = high
RNG1, RNG0 both not high
simultaneously
CONDITIONS
CC
- 0.3V. PWRDWN is ≤ 0.3V.
ID
⏐ = 0.1V to 1.2V, input common-mode voltage
0.35 x t
0.35 x t
2.575 x
28.57
0.4 x
0.4 x
MIN
-2.0
t
3.2
3.8
2.7
3.6
8.5
40
T
t
t
3
T
T
+
CC_
T
T
= +3.3V, ⏐V
0.45 x
0.45 x
0.4 x t
0.4 x t
TYP
50
t
t
T
T
T
T
16385 x
2.725 x
333.00
MAX
0.6 x
0.6 x
ID
+2.0
12.8
t
100
4.4
5.5
4.5
5.3
35
60
T
30
30
t
t
t
6
⏐ = 0.2V, V
T
T
T
+
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
CM
=