74LVC1G125GW-Q100, NXP Semiconductors, 74LVC1G125GW-Q100, Datasheet

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74LVC1G125GW-Q100,

Manufacturer Part Number
74LVC1G125GW-Q100,
Description
Buffers & Line Drivers
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74LVC1G125GW-Q100,

Rohs
yes
Number Of Input Lines
1
Number Of Output Lines
1
Polarity
Non-Inverting
Supply Voltage - Max
5.5 V
Supply Voltage - Min
1.65 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
TSSOP-5
Logic Family
74LVC
Logic Type
CMOS
Maximum Power Dissipation
250 mW
Minimum Operating Temperature
- 40 C
Output Type
3-State
Propagation Delay Time
10.5 ns
Supply Current
100 mA
1. General description
2. Features and benefits
The 74LVC1G125-Q100 provides one non-inverting buffer/line driver with 3-state output.
The 3-state output is controlled by the output enable input (OE). A HIGH-level at pin OE
causes the output to assume a high-impedance OFF-state.
The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
74LVC1G125-Q100
Bus buffer/line driver; 3-state
Rev. 1 — 9 July 2012
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
Complies with JEDEC standard:
24 mA output drive (V
ESD protection:
CMOS low power consumption
Inputs accept voltages up to 5 V
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Specified from 40 C to +85 C and from 40 C to +125 C
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 )
CC
= 3.0 V)
Product data sheet
OFF
. The I
OFF

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74LVC1G125GW-Q100, Summary of contents

Page 1

Bus buffer/line driver; 3-state Rev. 1 — 9 July 2012 1. General description The 74LVC1G125-Q100 provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE). A HIGH-level at pin OE ...

Page 2

... Type number Package Temperature range Name 40 C to +125 C 74LVC1G125GW-Q100 40 C to +125 C 74LVC1G125GV-Q100 4. Marking Table 2. Marking Type number 74LVC1G125GW-Q100 74LVC1G125GV-Q100 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram mna118 Fig 1 ...

Page 3

... NXP Semiconductors 6.2 Pin description Table 3. Pin description Symbol Pin GND Functional description [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level don’t care high-impedance OFF-state. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...

Page 4

... NXP Semiconductors 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/V input transition rise and fall rate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). ...

Page 5

... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I power-off leakage current V OFF I supply current CC I additional supply current CC C input capacitance I = 40 C to +125 C T amb V HIGH-level input voltage IH V LOW-level input voltage ...

Page 6

... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t propagation delay see enable time see disable time see dis ...

Page 7

... NXP Semiconductors 12. Waveforms Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 5. Input A to output Y propagation delay times OE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in ...

Page 8

... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 7. Test circuit for measuring switching times Table 10 ...

Page 9

... NXP Semiconductors 13. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1. DIMENSIONS (mm are the original dimensions UNIT max. 0.1 1.0 mm 1.1 0.15 0 0.8 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE ...

Page 10

... NXP Semiconductors Plastic surface-mounted package; 5 leads DIMENSIONS (mm are the original dimensions) UNIT 0.100 1.1 0.40 0.26 mm 0.013 0.9 0.25 0.10 OUTLINE VERSION IEC SOT753 Fig 9. Package outline SOT753 74LVC1G125_Q100 Product data sheet scale 3.1 1.7 3.0 0.6 0.95 2.7 1.3 2.5 0.2 REFERENCES ...

Page 11

... NXP Semiconductors 14. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic MIL Military 15. Revision history Table 12. Revision history Document ID Release date 74LVC1G125_Q100 v.1 20120709 74LVC1G125_Q100 ...

Page 12

... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 13

... NXP Semiconductors No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations ...

Page 14

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 13 Package outline ...

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