LPC1788FBD144,551 NXP Semiconductors, LPC1788FBD144,551 Datasheet - Page 86

• Manufacturer Part Number: LPC1788FBD144,551
• Description: 8-bit Microcontrollers - MCU CORTEX-M3 512KB FL 96KB SRAM 4KB EE USB
• Manufacturer: NXP Semiconductors

Specifications of LPC1788FBD144,551

• Rohs: yes
• Factory Pack Quantity: 60

NXP Semiconductors
LPC178X_7X
Product data sheet
Fig 19. Dynamic external memory interface signal timing
[1]
[2]
[3]
Table 20.
C
[1]
EMC_CKEOUTn,
EMC_DQMOUTn
Symbol
t
EMC_D[31:0]
read
d
L
EMC_D[31:0]
write
EMC_DYCSn,
EMC_A[22:0],
= 10 pF, T
Refers to SDRAM clock signal EMC_CLKx.
The data input set-up time has to be selected with the following margin:
t
The data input hold time has to be selected with the following margin:
t
The programmable delay blocks are controlled by the EMCDLYCTL register in the EMC register block. All
delay times are incremental delays for each element starting from delay block 0. See the LPC178x/7x user
manual for details.
EMC_RAS,
EMC_CAS,
su(D)
h(D)
EMC_CLKn
EMC_WE,
delay = 0
+ SDRAM access time - board delay time - delay time of feedback clock  0.
+ delay time of feedback clock  SDRAM access time  board delay time  0.
Parameter
delay time
Dynamic characteristics: Dynamic external memory interface programmable
clock delays
amb
=
All information provided in this document is subject to legal disclaimers.

40
Rev. 4.1 — 15 November 2012

C to 85
Conditions
Programmable delay block 0 (CMDDLY
or CLKOUTnDLY bit 0 = 1)
Programmable delay block 1 (CMDDLY
or CLKOUTnDLY bit 1 = 1)
Programmable delay block 2 (CMDDLY
or CLKOUTnDLY bit 2 = 1)
Programmable delay block 3 (CMDDLY
or CLKOUTnDLY bit 3 = 1)
Programmable delay block 4 (CMDDLY
or CLKOUTnDLY bit 4 = 1)
t
t
d(xV)
d(QV)

t
su(D)
C, V
DD(3V3)
t
h(x)
t
t
h(Q)
h(D)
= 3.0 V to 3.6 V.Values guaranteed by design.
32-bit ARM Cortex-M3 microcontroller
T
cy(clk)
002aah129
[1]
[1]
[1]
[1]
[1]
LPC178x/7x
Min
0.1
0.2
0.5
1.2
2.4
© NXP B.V. 2012. All rights reserved.
Max
0.2
0.5
1.3
2.9
6.0
86 of 120
Unit
ns
ns
ns
ns
ns