C8051T326-GMR Silicon Labs, C8051T326-GMR Datasheet - Page 153
C8051T326-GMR
Manufacturer Part Number
C8051T326-GMR
Description
8-bit Microcontrollers - MCU USB-OTP-16K-QFN28
Manufacturer
Silicon Labs
Datasheet
1.C8051T322-GQR.pdf
(292 pages)
Specifications of C8051T326-GMR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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SFR Definition 22.19. P2SKIP: Port 2 Skip
SFR Address = 0xD6
SFR Definition 22.20. P3: Port 3
SFR Address = 0xB0; Bit-Addressable
Name
Reset
Name
Reset
Bit
7:0
Bit
7:1
Type
Type
0
Bit
Bit
Unused
P2SKIP[7:0]
Name
P3[0]
Name
R
7
0
7
0
Unused.
Port 3 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Port 2 Crossbar Skip Enable Bits.
These bits select Port 2 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P2.n pin is not skipped by the Crossbar.
1: Corresponding P2.n pin is skipped by the Crossbar.
R
6
0
6
0
Description
R
5
0
5
0
C8051T620/621/320/321/322/323
Rev. 1.1
Don’t Care
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
R
4
0
4
0
P2SKIP[7:0]
R/W
Function
Write
R
3
0
3
0
R
2
0
2
0
0000000b
0: P3.0 Port pin is logic
LOW.
1: P3.0 Port pin is logic
HIGH.
R
1
0
1
0
Read
P3[0]
R/W
0
0
0
1
153
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