C8051F303-GSR Silicon Labs, C8051F303-GSR Datasheet - Page 122
C8051F303-GSR
Manufacturer Part Number
C8051F303-GSR
Description
8-bit Microcontrollers - MCU 8KB 14Pin MCU
Manufacturer
Silicon Labs
Datasheet
1.C8051F301-GSR.pdf
(178 pages)
Specifications of C8051F303-GSR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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C8051F300/1/2/3/4/5
13.4.3. Data Register
The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been
received. Software may safely read or write to the data register when the SI flag is set. Software should not
attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0,
as the interface may be in the process of shifting a byte of data into or out of the register.
Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received
data is located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously
being shifted in. SMB0DAT always contains the last data byte present on the bus. In the event of lost arbi-
tration, the transition from master transmitter to slave receiver is made with the correct data or address in
SMB0DAT.
122
Bits7–0: SMB0DAT: SMBus Data.
R/W
Bit7
The SMB0DAT register contains a byte of data to be transmitted on the SMBus serial inter-
face or a byte that has just been received on the SMBus serial interface. The CPU can read
from or write to this register whenever the SI serial interrupt flag (SMB0CN.0) is set to logic
one. The serial data in the register remains stable as long as the SI flag is set. When the SI
flag is not set, the system may be in the process of shifting data in/out and the CPU should
not attempt to access this register.
R/W
Bit6
SFR Definition 13.3.
R/W
Bit5
R/W
Bit4
Rev. 2.9
R/W
Bit3
SMB0DAT: SMBus Data
R/W
Bit2
R/W
Bit1
R/W
Bit0
SFR Address:
00000000
Reset Value
0xC2
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