74ALVCH16601DGG,11 NXP Semiconductors, 74ALVCH16601DGG,11 Datasheet - Page 2

• Manufacturer Part Number: 74ALVCH16601DGG,11
• Description: IC UNIV BUS TXRX 18BIT 56TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74ALVCHr

Specifications of 74ALVCH16601DGG,11

• Logic Type: Universal Bus Transceiver
• Package / Case: 56-TSSOP
• Number Of Circuits: 18-Bit
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Logic Family: ALVC
• Number Of Channels Per Chip: 18
• Input Level: LVTTL
• Output Level: LVTTL
• Output Type: 3-State
• High Level Output Current: - 24 mA
• Low Level Output Current: 24 mA
• Propagation Delay Time: 3.1 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Maximum Operating Temperature: + 85 C
• Function: Universal Bus Transceiver
• Input Bias Current (max): 40 uA
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Polarity: Non-Inverting
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74ALVCH16601DG; 74ALVCH16601DG; 935262546112

1. C
Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0V; T
NOTES:
ORDERING INFORMATION
56-Pin Plastic TSSOP Type II
1998 Sep 24
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
Direct interface with TTL levels
MULTIBYTE
Low inductance multiple V
and ground bounce
Current drive
All inputs have bus hold circuitry
Output drive capability 50 transmission lines @ 85 C
18-bit universal bus transceiver (3-State)
t
C
C
C
C
PHL
P
f
f
S (C
SYMBOL
i
o
I/O
I
PD
PD
D
= input frequency in MHz; C
= output frequency in MHz; V
= C
/t
L
PLH
is used to determine the dynamic power dissipation (P
PD
V
amb
CC
TM
V
2
PACKAGES
= 25 C; t
CC
24 mA at 3.0 V
flow-through standard pin-out architecture
Propagation delay
An, Bn to Bn, An
Input/Output capacitance
Input capacitance
Power dissipation capacitance per latch
Power dissipation capacitance per latch
f
2
o
) = sum of outputs.
f
i
+ S (C
r
= t
CC
f
= 2.5 ns
L
and ground pins for minimum noise
L
PARAMETER
V
= output load capacity in pF;
CC
CC
= supply voltage in V;
2
f
o
) where:
TEMPERATURE RANGE
–40 C to +85 C
D
in mW):
V
V
V = GND to V
V
CC
CC
I
= GND to V
= 2.5V, C
= 3.3V, C
2
DESCRIPTION
The 74ALVCH16601 is an 18-bit universal transceiver featuring
non-inverting 3-State bus compatible outputs in both send and
receive directions. Data flow in each direction is controlled by output
enable (OE
(CP
in the transparent mode when LE
A data is latched if CP
is Low, the A-bus data is stored in the latch/flip-flop on the
Low-to-High transition of CP
active. When OE
state. The clocks can be controlled with the clock-enable inputs
(CE
Data flow for B-to-A is similar to that of A-to-B but uses OE
and CP
To ensure the high impedance state during power up or power
down, OE
resistor; the minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
AB
BA
L
L
CC
CC
= 30pF
= 50pF
/CE
and CP
1
1
BA
CONDITIONS
OUTSIDE NORTH AMERICA
.
BA
AB
AB
).
and OE
74ALVCH16601 DGG
BA
and OE
) inputs. For A-to-B data flow, the device operates
AB
Outputs enabled
Outputs disabled
is High, the outputs are in the high-impedance
AB
AB
BA
should be tied to V
), latch enable (LE
is held at a High or Low logic level. If LE
AB
. When OE
AB
is High. When LE
74ALVCH16601
AB
CC
TYPICAL
AB
is Low, the outputs are
through a pullup
Product specification
and LE
3.1
2.8
8.0
4.0
21
3
DWG NUMBER
SOT364-1
853-2122 20076
BA
AB
), and clock
is Low, the
UNIT
BA
pF
pF
pF
pF
ns
, LE
BA
AB