XRT91L32ES Exar, XRT91L32ES Datasheet - Page 20

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XRT91L32ES

Manufacturer Part Number
XRT91L32ES
Description
LIN Transceivers SONET SDH 8 bit TRANCEIVER
Manufacturer
Exar
Datasheet

Specifications of XRT91L32ES

Product Category
LIN Transceivers
Rohs
yes
XRT91L32
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
The 8-bit Single-Ended LVTTL running at 77.76 Mbps (STS-12/STM-4) or 19.44 Mbps (STS-3/STM-1) parallel
data output of the receive path is used to interface to a SONET Framer/ASIC synchronized to the recovered
clock. A simplified block diagram is shown in Figure 9.
F
The parallel receiver outputs are automatically pulled "Low" or forced to a logic state of "0" during a LOS
condition to prevent data chattering unless LOS detection is disabled by asserting DLOSDIS and keeping
LOSEXT input pin "high." In addition, the user can also assert LOSEXT input pin "low" from the optical module
to force an LOS and mute the parallel receiver outputs as well (while DLOSDIS input is also low, see Figure 7.)
2.8
2.9
IGURE
9. R
Receive Parallel Output Interface
Disable Parallel Receive Data Output Upon LOS
ECEIVE
P
ARALLEL
O
UTPUT
SONET Framer/ASIC
I
NTERFACE
B
LOCK
8
18
RXDO[7:0]
RXPCLKO
STS-12/STM-4
STS-3/STM-1
Transceiver
XRT91L32
or
xr
REV. 1.0.2

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