74HC299DB,112 NXP Semiconductors, 74HC299DB,112 Datasheet - Page 13
![IC UNIV SHIFT REGISTER 20SSOP](/photos/6/52/65221/20-ssop_sot339-1_sml.jpg)
74HC299DB,112
Manufacturer Part Number
74HC299DB,112
Description
IC UNIV SHIFT REGISTER 20SSOP
Manufacturer
NXP Semiconductors
Series
74HCr
Datasheets
1.74HCT4046ADB112.pdf
(19 pages)
2.74HCT4046ADB112.pdf
(23 pages)
3.74HC299N652.pdf
(24 pages)
Specifications of 74HC299DB,112
Number Of Circuits
8-Bit
Package / Case
20-SSOP
Logic Type
Universal Shift Register, CMOS
Current - Output High, Low
6mA, 6mA
Voltage - Supply
2 V ~ 6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Counting Sequence
Serial/Parallel to Serial/Parallel
Logic Family
74HC
Propagation Delay Time
200 ns, 40 ns, 34 ns
Supply Voltage (max)
6 V
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
2 V to 6 V
Output Type
3-State
Function
Shift Register
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-2661-5
935189890112
935189890112
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
74HC299DB,112
Manufacturer:
MICREL
Quantity:
1 401
Philips Semiconductors
AC waveforms 74HCT
Test circuit for 74HCT
March 1988
handbook, full pagewidth
HCMOS family characteristics
C
R
(1) In Fig.9 the active transition of the clock is going from LOW-to-HIGH and the active level of the forcing signals
(2) For AC measurements: t
Fig.9
L
T
(SET, RESET and PRESET) is HIGH. The actual direction of the transition of the clock input and the actual
active levels of the forcing signals are specified in the individual device data sheet.
=
=
Set-up times, hold times, removal times, propagation delays and the maximum clock pulse frequency for
sequential logic ICs.
load capacitance including jig and probe capacitance (see AC
CHARACTERISTICS for values).
termination resistance should be equal to the output impedance Z
the pulse generator.
OUTPUT
PRESET
CLOCK
RESET,
r
INPUT
INPUT
INPUT
DATA
SET,
= t
f
= 6 ns; when measuring f
handbook, halfpage
GENERATOR
10%
1.3 V
PULSE
t su
t rem
1.3 V
t r
10%
1.3 V
t PLH
90%
t WH
max
Fig.10 Test circuit.
1.3 V
V I
90%
t h
, there is no constraint on t
1/f max
t TLH
t f
R T
13
t WL
o
D.U.T
V CC
t su
of
t PHL
V O
r
, t
f
with 50% duty factor.
C L
t h
FAMILY SPECIFICATIONS
t THL
MGK565
50 pF
MGK568
3 V
GND
3 V
GND
3 V
GND