74AUP2G3404GF,125 NXP Semiconductors, 74AUP2G3404GF,125 Datasheet

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74AUP2G3404GF,125

Manufacturer Part Number
74AUP2G3404GF,125
Description
Buffers & Line Drivers Lo-Pwr buffer & inverter
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74AUP2G3404GF,125

Rohs
yes
Number Of Input Lines
2
Number Of Output Lines
2
Supply Voltage - Max
3.6 V
Supply Voltage - Min
1.1 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
XSON-6
Logic Family
AUP
Maximum Power Dissipation
250 mW
Minimum Operating Temperature
- 40 C
Number Of Channels Per Chip
1
Output Type
CMOS
Propagation Delay Time
11.4 ns
Supply Current
0.5 uA
1. General description
2. Features and benefits
The 74AUP2G3404 is a single buffer and single inverter.
Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall
times across the entire V
This device ensures a very low static and dynamic power consumption across the entire
V
This device is fully specified for partial power-down applications using I
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
CC
74AUP2G3404
Low-power buffer and inverter
Rev. 1 — 22 August 2012
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
ESD protection:
Low static power consumption; I
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
I
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
OFF
range from 0.8 V to 3.6 V.
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
circuitry provides partial power-down mode operation
CC
range from 0.8 V to 3.6 V.
CC
= 0.9 A (maximum)
CC
Product data sheet
OFF
. The I
OFF

Related parts for 74AUP2G3404GF,125

74AUP2G3404GF,125 Summary of contents

Page 1

Low-power buffer and inverter Rev. 1 — 22 August 2012 1. General description The 74AUP2G3404 is a single buffer and single inverter. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range 40 C to +125 C 74AUP2G3404GW 40 C to +125 C 74AUP2G3404GM 40 C to +125 C 74AUP2G3404GF 40 C to +125 C 74AUP2G3404GN 40 C to +125 C 74AUP2G3404GS 4. Marking Table 2. Marking Type number ...

Page 3

... NXP Semiconductors 6. Pinning information 6.1 Pinning 74AUP2G3404 GND aaa-002993 Fig 4. Pin configuration SOT363 6.2 Pin description Table 3. Pin description Symbol Pin Description 1A 1 data input GND 2 ground ( data input 2Y 4 data output V 5 supply voltage ...

Page 4

... NXP Semiconductors 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK V input voltage I I output clamping current OK V output voltage O I output current ...

Page 5

... NXP Semiconductors 10. Static characteristics Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = 25 C T amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I power-off leakage current OFF  ...

Page 6

... NXP Semiconductors Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = 40 C to +85 C T amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I power-off leakage current OFF  ...

Page 7

... NXP Semiconductors Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = 40 C to +125 C T amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I power-off leakage current OFF  ...

Page 8

... NXP Semiconductors 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions propagation 2Y; see pd delay 3.6 V ...

Page 9

... NXP Semiconductors Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions pF and power MHz dissipation capacitance ...

Page 10

... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 8. Test circuit for measuring switching times Table 11 ...

Page 11

... NXP Semiconductors 13. Package outline Plastic surface-mounted package; 6 leads y 6 pin 1 index DIMENSIONS (mm are the original dimensions UNIT max 1.1 0.30 0.25 mm 0.1 0.8 0.20 0.10 OUTLINE VERSION IEC SOT363 Fig 9. Package outline SOT363 (SC-88) 74AUP2G3404 Product data sheet scale ...

Page 12

... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1. (2) terminal 1 index area Dimensions (mm are the original dimensions) (1) Unit max 0.5 0.04 0.25 1.50 mm nom 0.20 1.45 min 0.17 1.40 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. Outline version ...

Page 13

... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 0 6× (1) terminal 1 index area DIMENSIONS (mm are the original dimensions UNIT b D max max 0.20 1.05 mm 0.5 0.04 0.12 0.95 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION IEC SOT891 Fig 11. Package outline SOT891 (XSON6) ...

Page 14

... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 0.95 mm nom 0.15 0.90 min 0.12 0.85 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version IEC SOT1115 Fig 12. Package outline SOT1115 (XSON6) ...

Page 15

... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.05 mm nom 0.15 1.00 min 0.12 0.95 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version IEC SOT1202 Fig 13. Package outline SOT1202 (XSON6) ...

Page 16

... NXP Semiconductors 14. Abbreviations Table 12. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 13. Revision history Document ID Release date 74AUP2G3404 v.1 20120822 74AUP2G3404 Product data sheet Data sheet status Product data sheet All information provided in this document is subject to legal disclaimers ...

Page 17

... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 18

... Product data sheet NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

Page 19

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Package outline ...

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