74HC595D-Q100 NXP Semiconductors, 74HC595D-Q100 Datasheet - Page 5

• Manufacturer Part Number: 74HC595D-Q100
• Description: Counter Shift Registers 8 Bit Par-Ser Out 6V
• Manufacturer: NXP Semiconductors

Specifications of 74HC595D-Q100

• Rohs: yes
• Package / Case: SO-16
• Logic Family: 74HC
• Logic Type: Shift Register
• Output Type: Parallel / Serial
• Propagation Delay Time: 265 ns
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Function: 8 Bit Parallel In Serial Out
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2 V to 6 V
• Product: Driver ICs - Various
• Supply Voltage - Max: 6 V
• Supply Voltage - Min: 2 V
• Part # Aliases: 74HC595D-Q100,118

NXP Semiconductors
Table 2.
7. Functional description
Table 3.
[1]
74HC_HCT595_Q100
Product data sheet
Symbol
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
GND
Q7S
MR
SHCP
STCP
OE
DS
V
Control
SHCP STCP OE
X
X
X

X

CC
H = HIGH voltage state;
L = LOW voltage state;
 = LOW-to-HIGH transition;
X = don’t care;
NC = no change;
Z = high-impedance OFF-state.
X

X
X


Pin description
Function table
L
L
H
L
L
L
6.2 Pin description
MR
L
L
L
H
H
H
[1]
Input
DS
X
X
X
H
X
X
Pin
8
10
11
13
14
16
15, 1, 2, 3, 4, 5, 6, 7
9
12
Output
Q7S
L
L
L
Q6S
NC
Q6S
All information provided in this document is subject to legal disclaimers.
8-bit serial-in, serial or parallel-out shift register with output latches;
74HC595-Q100; 74HCT595-Q100
Qn
NC
L
Z
NC
QnS
QnS
Rev. 2 — 10 April 2013
Function
a LOW-level on MR only affects the shift registers
empty shift register loaded into storage register
shift register clear; parallel outputs in high-impedance OFF-state
logic HIGH-level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).
contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages
contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
Description
parallel data output
ground (0 V)
serial data output
master reset (active LOW)
shift register clock input
storage register clock input
output enable input (active LOW)
serial data input
supply voltage
© NXP B.V. 2013. All rights reserved.
3-state
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