74HC00D-Q100 NXP Semiconductors, 74HC00D-Q100 Datasheet

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74HC00D-Q100

Manufacturer Part Number
74HC00D-Q100
Description
Logic Gates 2-IN AND Gate 6V
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74HC00D-Q100

Product
AND
Logic Family
74HC
Number Of Gates
4
Number Of Lines (input / Output)
2 /
Propagation Delay Time
135 ns
Supply Voltage - Max
6 V
Supply Voltage - Min
2 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SO-14
Maximum Power Dissipation
500 mW
Minimum Operating Temperature
- 40 C
Number Of Input Lines
2
Operating Temperature Range
- 40 C to + 125 C
Output Current
25 mA
Power Dissipation
500 mW
Part # Aliases
74HC00D-Q100,118
1. General description
2. Features and benefits
The 74HC00-Q100; 74HCT00-Q100 are high-speed Si-gate CMOS devices that comply
with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL
(LSTTL).
The 74HC00-Q100; 74HCT00-Q100 provides a quad 2-input NAND function.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
74HC00-Q100; 74HCT00-Q100
Quad 2-input NAND gate
Rev. 1 — 12 July 2012
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Input levels:
ESD protection:
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
For 74HC00-Q100: CMOS level
For 74HCT00-Q100: TTL level
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 )
Product data sheet

Related parts for 74HC00D-Q100

74HC00D-Q100 Summary of contents

Page 1

Quad 2-input NAND gate Rev. 1 — 12 July 2012 1. General description The 74HC00-Q100; 74HCT00-Q100 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL). The ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 40 C to +125 C 74HC00D-Q100 74HCT00D-Q100 40 C to +125 C 74HC00PW-Q100 74HCT00PW-Q100 40 C to +125 C 74HC00BQ-Q100 74HCT00BQ-Q100 4. Functional diagram ...

Page 3

... NXP Semiconductors 5. Pinning information 5.1 Pinning 74HC00-Q100 74HCT00-Q100 GND 7 Fig 4. Pin configuration SO14 and TSSOP14 5.2 Pin description Table 2. Pin description Symbol Pin 10 GND Functional description [1] Table 3 ...

Page 4

... NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK I output clamping current OK I output current O I supply current CC I ground current ...

Page 5

... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74HC00-Q100 V HIGH-level input voltage LOW-level input voltage HIGH-level output voltage =  ...

Page 6

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74HCT00-Q100 V HIGH-level input voltage V LOW-level input voltage V HIGH-level output voltage = 20  4 LOW-level ...

Page 7

... NXP Semiconductors Table 7. Dynamic characteristics GND = pF; for load circuit see L Symbol Parameter Conditions 74HCT00-Q100 t propagation delay nA nY; see transition time power dissipation per package; PD capacitance the same as t and PHL PLH ...

Page 8

... NXP Semiconductors Test data is given in Table Definitions test circuit termination resistance should be equal to output impedance load capacitance including jig and probe capacitance. L Fig 7. Test circuit for measuring switching times Table 9. Test data Type Input V I 74HC00-Q100 V CC 74HCT00-Q100 3.0 V 74HC_HCT00_Q100 Product data sheet 74HC00-Q100 ...

Page 9

... NXP Semiconductors 12. Package outline SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 10

... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 11

... NXP Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 12

... NXP Semiconductors 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model TTL Transistor-Transistor Logic MIL Military 14. Revision history Table 11. Revision history Document ID Release date 74HC_HCT00_Q100 v ...

Page 13

... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 14

... NXP Semiconductors No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations ...

Page 15

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 3 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Abbreviations ...

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