74AUP1T34GM-G NXP Semiconductors, 74AUP1T34GM-G Datasheet - Page 2

• Manufacturer Part Number: 74AUP1T34GM-G
• Description: Buffers & Line Drivers 1.8V SINGLE INVERTER (UNBUFF)
• Manufacturer: NXP Semiconductors

Specifications of 74AUP1T34GM-G

• Product Category: Buffers & Line Drivers
• Rohs: yes
• Number Of Input Lines: 3
• Number Of Output Lines: 1
• Polarity: Non-Inverting
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.1 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-886-6
• High Level Output Current: - 4 mA
• Logic Family: AUP
• Logic Type: CMOS
• Low Level Output Current: 4 mA
• Minimum Operating Temperature: - 40 C
• Number Of Channels Per Chip: 1
• Propagation Delay Time: 32.9 ns at 1.1 V to 1.3 V
• Factory Pack Quantity: 5000
• Part # Aliases: 74AUP1T34GM,115

NXP Semiconductors
3. Ordering information
Table 1.
4. Marking
Table 2.
[1]
5. Functional diagram
74AUP1T34
Product data sheet
Type number
74AUP1T34GW
74AUP1T34GM
74AUP1T34GF
74AUP1T34GN
74AUP1T34GS
Type number
74AUP1T34GW
74AUP1T34GM
74AUP1T34GF
74AUP1T34GN
74AUP1T34GS
Fig 1.
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
Logic symbol
2
Ordering information
Marking
A
001aac538
Package
Temperature range Name
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
Y
4
All information provided in this document is subject to legal disclaimers.
Fig 2.
TSSOP5
XSON6
XSON6
XSON6
XSON6
Rev. 4 — 16 March 2012
IEC logic symbol
2
Description
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
plastic extremely thin small outline package; no leads;
6 terminals; body 1  1.45  0.5 mm
plastic extremely thin small outline package; no leads;
6 terminals; body 1  1  0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9  1.0  0.35 mm
extremely thin small outline package; no leads;
6 terminals; body 1.0  1.0  0.35 mm
001aac537
Marking code
pQ
pQ
pQ
pQ
pQ
4
Low-power dual supply translating buffer
[1]
Fig 3.
A
Logic diagram
74AUP1T34
© NXP B.V. 2012. All rights reserved.
001aac536
Version
SOT353-1
SOT886
SOT891
SOT1115
SOT1202
Y
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