DS3508E+T&R/C Maxim Integrated, DS3508E+T&R/C Datasheet - Page 11

• Manufacturer Part Number: DS3508E+T&R/C
• Description: LCD Gamma Buffers I2C 8Ch Gamma Buffer w/EEPROM
• Manufacturer: Maxim Integrated

Specifications of DS3508E+T&R/C

• Rohs: yes
• Factory Pack Quantity: 2500
• Part # Aliases: 90-3508F+C00

The following terminology is commonly used to describe
I
Characteristics table for additional information.)
Master device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses and START and STOP conditions.
Slave devices: Slave devices send and receive data at
the master’s request.
Bus idle or not busy: Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic-high states.
START condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition.
STOP condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition.
Repeated START condition: The master can use a
repeated START condition at the end of one data trans-
fer to indicate that it will immediately initiate a new data
transfer following the current one. Repeated STARTS are
commonly used during read operations to identify a spe-
cific memory address to begin a data transfer. A repeat-
ed START condition is issued identically to a normal
START condition.
Figure 4. I
2
C data transfers. (See Figure 4 and the I
SDA
SCL
NOTE: TIMING IS REFERENCED TO V
I
2
C Serial Interface Description
STOP
2
C Timing Diagram
I
2
t
BUF
C, 8-Channel Gamma Buffer with EEPROM
START
______________________________________________________________________________________
IL(MAX)
t
t
HD:STA
LOW
AND V
IH(MIN)
.
I
t
2
R
t
HD:DAT
C Definitions
2
C Electrical
t
F
t
HIGH
t
SU:DAT
Bit write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements. Data is shifted into the
device during the rising edge of the SCL.
Bit read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time before the next rising edge of SCL during a
bit read. The device shifts out each bit of data on SDA at
the falling edge of the previous SCL pulse and the data
bit is valid at the rising edge of the current SCL pulse.
Remember that the master generates all SCL clock puls-
es, including when it is reading bits from the slave.
Acknowledge (ACK and NACK): An Acknowledge
(ACK) or Not Acknowledge (NACK) is always the 9th bit
transmitted during a byte transfer. The device receiving
data (the master during a read or the slave during a
write operation) performs an ACK by transmitting a 0
during the 9th bit. A device performs a NACK by trans-
mitting a 1 during the 9th bit. Timing for the ACK and
NACK is identical to all other bit writes. An ACK is the
acknowledgment that the device is properly receiving
data. A NACK is used to terminate a read sequence or
indicates that the device is not receiving data.
Byte write: A byte write consists of 8 bits of information
transferred from the master to the slave (most signifi-
cant bit first) plus a 1-bit acknowledgment from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgment is read using the bit read definition.
REPEATED
START
t
SU:STA
t
HD:STA
t
SP
t
SU:STO
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