72V3644L10PF IDT, 72V3644L10PF Datasheet - Page 17

• Manufacturer Part Number: 72V3644L10PF
• Description: FIFO
• Manufacturer: IDT

Specifications of 72V3644L10PF

• Part # Aliases: IDT72V3644L10PF

NOTES:
1. FIFO2 Master Reset (MRS2) is performed in the same manner to load X2 and Y2 with a preset value. For FIFO2 Master Reset, MRS1 must toggle simultaneously with MRS2.
2. PRS1 must be HIGH during Master Reset.
3. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
NOTES:
1. Partial Reset is performed in the same manner for FIFO2.
2. MRS1 must be HIGH during Partial Reset.
3. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
EFB/ORB
EFB/ORB
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
BE/FWFT
FS1,FS0
FFA/IRA
FFA/IRA
CLKA
CLKB
MRS1
CLKA
CLKB
MBF1
MBF1
PRS1
SPM
AEB
AFA
AEB
AFA
Figure 3. FIFO1 Master Reset and Loading X1 and Y1 with a Preset Value of Eight
t
t
RSTS
RSTS
t
t
t
t
t
t
RSF
RSF
RSF
RSF
RSF
RSF
Figure 4. FIFO1 Partial Reset
t
t
WFF
WFF
TM
WITH BUS-MATCHING
(1)
17
(IDT Standard and FWFT Modes)
t
t
SPMS
FSS
t
BES
t
t
REF
REF (3)
(3)
0,1
BE
t
RSTH
t
RSTH
(1)
t
BEH
t
t
FSH
SPMH
(IDT Standard and FWFT Modes)
COMMERCIAL TEMPERATURE RANGE
t
FWS
FWFT
t
WFF
t
WFF
4664 drw05
4664 drw06