72V3644L10PF IDT, 72V3644L10PF Datasheet - Page 28

• Manufacturer Part Number: 72V3644L10PF
• Description: FIFO
• Manufacturer: IDT

Specifications of 72V3644L10PF

• Part # Aliases: IDT72V3644L10PF

NOTES:
1. t
2. If Port B size is word or byte, IRB is set LOW by the last word or byte write of the long word, respectively.
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
A0-A35
B0-B35
CLKA
CLKB
CLKB edge is less than t
W/RA
W/RB
SKEW1
MBA
ORA
MBB
ENA
ENB
CSA
CSB
IRB
is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
LOW
LOW
FIFO2 FULL
LOW
LOW
LOW
HIGH
Previous Word in FIFO2 Output Register
t
CLKH
SKEW1
t
CLK
, then IRB may transition HIGH one CLKB cycle later than shown.
t
Figure 21. IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)
ENS2
t
CLKL
t
t
SKEW1
ENH
t
A
(1)
1
TM
t
CLKH
WITH BUS-MATCHING
t
CLK
28
t
CLKL
2
Next Word From FIFO2
t
WFF
t
t
ENS2
ENS2
t
DS
COMMERCIAL TEMPERATURE RANGE
To FIFO2
Write
t
t
WFF
DH
t
t
ENH
ENH
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