74AUP1G240GW-G NXP Semiconductors, 74AUP1G240GW-G Datasheet - Page 16
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74AUP1G240GW-G
Manufacturer Part Number
74AUP1G240GW-G
Description
Buffers & Line Drivers 3V SINGLE BUF/LD INV 3S
Manufacturer
NXP Semiconductors
Datasheet
1.74AUP1G240GW-G.pdf
(23 pages)
Specifications of 74AUP1G240GW-G
Product Category
Buffers & Line Drivers
Rohs
yes
Number Of Input Lines
1
Number Of Output Lines
1
Polarity
Inverting
Supply Voltage - Max
3.6 V
Supply Voltage - Min
0.8 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
UMT-5
High Level Output Current
- 4 mA
Logic Family
AUP
Logic Type
CMOS
Low Level Output Current
4 mA
Minimum Operating Temperature
- 40 C
Number Of Channels Per Chip
1
Output Type
3-State
Propagation Delay Time
21.6 ns at 1.1 V to 1.3 V, 12.3 ns at 1.4 V to 1.6 V, 9.5 ns at 1.65 V to 1.95 V, 7.1 ns at 2.3 V to 2.7 V, 6.4 ns at 3 V to 3.6 V
Factory Pack Quantity
3000
Part # Aliases
74AUP1G240GW,125
NXP Semiconductors
Fig 13. Package outline SOT891 (XSON6)
74AUP1G240
Product data sheet
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
DIMENSIONS (mm are the original dimensions)
Note
1. Can be visible in some manufacturing processes.
UNIT
mm
VERSION
OUTLINE
SOT891
max
0.5
A
max
0.04
A
1
0.20
0.12
e
b
terminal 1
index area
6×
IEC
(1)
L
1.05
0.95
1
D
1.05
0.95
E
0
1
6
JEDEC
0.55
e
All information provided in this document is subject to legal disclaimers.
e
1
REFERENCES
D
0.35
2
5
e
1
e
Rev. 4 — 29 June 2012
1
0.35
0.27
L
b
3
4
JEITA
0.40
0.32
scale
L
1
1
A
1
E
L
A
Low-power inverting buffer/line driver; 3-state
4×
(1)
2 mm
PROJECTION
EUROPEAN
74AUP1G240
© NXP B.V. 2012. All rights reserved.
ISSUE DATE
05-04-06
07-05-15
SOT891
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