MAX9972ACCS+DW Maxim Integrated, MAX9972ACCS+DW Datasheet - Page 19

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MAX9972ACCS+DW

Manufacturer Part Number
MAX9972ACCS+DW
Description
Buffers & Line Drivers
Manufacturer
Maxim Integrated
Datasheet

Specifications of MAX9972ACCS+DW

Rohs
yes
A CMOS-compatible serial interface controls the
MAX9972 modes (Figure 4). Control data flow into a 12-
bit shift register (LSB first) and are latched when CS is
taken high. Data from the shift register are then loaded
to the per-channel control latches as determined by
bits D8–D11, and indicated in Figure 4 and Table 4.
Figure 4. Serial Interface
Table 4. Control Register Bit Functions
BIT
10
11
0
1
2
3
4
5
6
7
8
9
SCLK
Serial Interface and Device Control
DIN
CS
LD
LOAD EN HIGH
LOAD EN LOW
FORCE EN
SENSE EN
LLEAK
NAME
TERM
CH1
CH2
CH3
CH4
______________________________________________________________________________________
Quad, Ultra-Low-Power, 300Mbps ATE
0–5
8
Update Channel 1 Control Register
Update Channel 2 Control Register
Update Channel 3 Control Register
Update Channel 4 Control Register
D
ENABLE
QUAD F/F
ENABLE
LOAD
Assert Low-Leakage Mode
Enable High Load Resistor
Enable Low Load Resistor
Enable Sense Switch
Enable Force Switch
Term Mode Control
Q
CHANNEL 1
MODE BITS
FUNCTION
11
Unused
Unused
6
10
0–5
9
D
9
QUAD F/F
ENABLE
LOAD
8
Q
MAX9972
MODE BITS
CHANNEL 2
The latches contain the six mode bits for each channel
of the device. The mode bits, in conjunction with exter-
nal inputs DATA_ and RCV_, manage the features of
each channel. Transfer data asynchronously from the
input registers to the channel registers by forcing LD
low. With LD always low, data transfer on the rising
edge of CS.
7
6
High Impedance
6
0–5
Term Mode
Drivers/Comparators
10
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
D
0
X
X
5
QUAD F/F
ENABLE
LOAD
BIT STATE
4
Q
MODE BITS
CHANNEL 3
3
6
Low Leakage
Term Mode
2
0–5
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
11
D
1
X
X
1
QUAD F/F
ENABLE
LOAD
0
Q
MODE BITS
CHANNEL 4
6
POWER-UP
STATE
0
0
0
0
0
0
0
0
1
1
1
1
19

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