PCF8576CT/S480/1,1 NXP Semiconductors, PCF8576CT/S480/1,1 Datasheet
PCF8576CT/S480/1,1
Related parts for PCF8576CT/S480/1,1
PCF8576CT/S480/1,1 Summary of contents
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PCF8576C Universal LCD driver for low multiplex rates Rev. 11 — 30 March 2012 1. General description The PCF8576C is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) multiplexed LCD containing up to four backplanes and ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Name PCF8576CHL/1 LQFP64 PCF8576CT/1 VSO56 PCF8576CTT/1 HTSSOP56 PCF8576CU/F1 PCF8576CU PCF8576CU/2/F2 PCF8576CU/2 [1] Delivery form: chip in tray. 4. Marking Table 2. Type number PCF8576CHL/1 PCF8576CT/1 PCF8576CTT/1 PCF8576CU/F1 PCF8576CU/2/F2 PCF8576C Product data sheet Universal LCD driver for low multiplex rates Description plastic low profile quad flat package ...
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... NXP Semiconductors 5. Block diagram V DD LCD BIAS GENERATOR V LCD CLK TIMING BLINKER SYNC OSC OSCILLATOR POWER- ON RESET V SS SCL INPUT FILTERS CONTROLLER SDA Fig 1. Block diagram of PCF8576C PCF8576C Product data sheet Universal LCD driver for low multiplex rates BP0 BP2 BP1 BP3 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Top view. For mechanical details, see Fig 2. Pin configuration for LQFP64 (PCF8576CHL/1) PCF8576C Product data sheet Universal LCD driver for low multiplex rates n. S34 S35 3 S36 4 S37 5 6 S38 7 S39 n.c. 8 PCF8576CHL n.c. 9 SDA 10 11 SCL 12 SYNC ...
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... NXP Semiconductors Top view. For mechanical details, see Fig 3. Pin configuration for VSO56 (PCF8576CT/1) PCF8576C Product data sheet Universal LCD driver for low multiplex rates 1 SDA 2 SCL SYNC 3 CLK OSC SA0 LCD BP0 ...
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... NXP Semiconductors Top view. For mechanical details, see Fig 4. Pin configuration for HTSSOP56 (PCF8576CTT/1) PCF8576C Product data sheet Universal LCD driver for low multiplex rates 1 SDA 2 SCL SYNC 3 CLK OSC SA0 LCD BP0 ...
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... NXP Semiconductors Viewed from pin side. For mechanical details, see Fig 5. Pin locations of PCF8576CU/F1 and PCF8576CU/2/F2 PCF8576C Product data sheet Universal LCD driver for low multiplex rates S18 35 S19 36 S20 37 S21 38 S22 39 S23 40 S24 ...
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... NXP Semiconductors 6.2 Pin description Table 3. Pin description Symbol Pin LQFP64 VSO56 (PCF8576CHL) (PCF8576CT) SDA 10 1 SCL 11 2 SYNC 12 3 CLK OSC SA0 LCD BP0, BP2 BP1, BP3 ...
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... NXP Semiconductors 7. Functional description The PCF8576C is a versatile peripheral device designed to interface between any microprocessor or microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure backplanes and segments. Fig 6. Example of displays suitable for PCF8576C The possible display configurations of the PCF8576C depend on the number of active backplane outputs required ...
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... NXP Semiconductors V DD PROCESSOR/ CONTROLLER V SS Fig 7. Typical system configuration The host microprocessor or microcontroller maintains the 2-line I channel with the PCF8576C. Biasing voltages for the multiplexed LCD waveforms are generated internally, removing the need for an external bias generator. The internal oscillator is selected by connecting ...
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... NXP Semiconductors 7.3 LCD voltage selector The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the mode-set command from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of ...
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... NXP Semiconductors Using Equation 1 ⁄ bias ⁄ bias is 2 The advantage of these LCD drive modes is a reduction of the LCD full scale voltage V as follows: • 1:3 multiplex ( • 1:4 multiplex ( These compare with It should be noted that V 7.3.1 Electro-optical performance Suitable values for V RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of the pixel ...
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... NXP Semiconductors Fig 8. Electro-optical characteristic: relative transmission curve of the liquid PCF8576C Product data sheet Universal LCD driver for low multiplex rates 100 % th(off) OFF GREY SEGMENT SEGMENT All information provided in this document is subject to legal disclaimers. Rev. 11 — 30 March 2012 PCF8576C ...
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... NXP Semiconductors 7.4 LCD drive mode waveforms 7.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown Fig 9. Static drive mode waveforms PCF8576C Product data sheet ...
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... NXP Semiconductors 7.4.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCF8576C allows the use Fig 10. Waveforms for the 1:2 multiplex drive mode with PCF8576C Product data sheet Universal LCD driver for low multiplex rates ...
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... NXP Semiconductors Fig 11. Waveforms for the 1:2 multiplex drive mode with PCF8576C Product data sheet Universal LCD driver for low multiplex rates V LCD LCD BP0 LCD LCD LCD BP1 LCD LCD LCD ...
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... NXP Semiconductors 7.4.3 1:3 Multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies as shown in Figure BP0 BP1 BP2 S n+1 S n+2 state 1 state Fig 12. Waveforms for the 1:3 multiplex drive mode with PCF8576C Product data sheet Universal LCD driver for low multiplex rates 12 ...
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... NXP Semiconductors 7.4.4 1:4 multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as shown in Figure BP0 BP1 BP2 BP3 Sn Sn+1 Sn+2 Sn+3 state 1 state Fig 13. Waveforms for the 1:4 multiplex mode with PCF8576C Product data sheet Universal LCD driver for low multiplex rates 13 ...
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... NXP Semiconductors 7.5 Oscillator The internal logic and the LCD drive signals of the PCF8576C are timed by the frequency f , which equals either the built-in oscillator frequency f clk f . clk(ext) The clock frequency (f for data reception from the I rate of 100 kHz, f 7.5.1 Internal clock The internal oscillator is enabled by connecting pin OSC to pin V output from pin CLK is the clock signal for any cascaded PCF8576C in the system ...
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... NXP Semiconductors The lower clock frequency has the disadvantage of increasing the response time when large amounts of display data are transmitted on the I process a display data byte before the next one arrives, it holds the SCL line LOW until the first display data byte is stored. This slows down the transmission rate of the I but no data loss occurs ...
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... NXP Semiconductors The display RAM bit map backplane outputs BP0 to BP3, and the columns which correspond with the segment outputs S0 to S39. In multiplexed LCD applications the segment data of the first, second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2, and BP3 respectively ...
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LCD segments LCD backplanes S a n+2 BP0 n+3 n+1 static n+5 n n+6 ...
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... NXP Semiconductors The following applies to • In the static drive mode, the eight transmitted data bits are placed in row 0 of eight successive 4-bit RAM words. • In the 1:2 multiplex mode, the eight transmitted data bits are placed in pairs into row 0 and 1 of four successive 4-bit RAM words. ...
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... NXP Semiconductors 7.14 Bank selector 7.14.1 Output bank selector The output bank selector (see address for transfer to the display register. The actual row selected depends on the LCD drive mode in operation and on the instant in the multiplex sequence. • In 1:4 multiplex mode: all RAM addresses of row 0 are selected, followed sequentially by the contents of row 1, row 2, and then row 3. • ...
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... NXP Semiconductors In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of LCD segments can be blinked by selectively changing the display RAM data at fixed time intervals. If the entire display needs to be blinked at a frequency other than the nominal blink frequency, this can be done using the mode-set command to set and reset the display enable bit E at the required rate (see 7 ...
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... NXP Semiconductors 7.16.3 System configuration A device generating a message is a transmitter and a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves. The system configuration is illustrated in Figure 18. TRANSMITTER/ SDA SCL Fig 18 ...
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... NXP Semiconductors data output by transmitter data output by receiver SCL from Fig 19. Acknowledgement of the I 7.16.5 PCF8576C I The PCF8576C acts transmit data the acknowledge signals of the selected devices. Device selection depends on the 2 I C-bus slave address, the transferred command data and the hardware subaddress. ...
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... NXP Semiconductors 2 The I C-bus protocol is shown in condition (S) from the I slave addresses available. All PCF8576Cs with the corresponding SA0 level acknowledge in parallel with the slave address but all PCF8576Cs with the alternative SA0 level ignore the whole I After acknowledgement, one or more command bytes follow which define the status of the addressed PCF8576Cs ...
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... NXP Semiconductors Table 8. Command Bit mode-set load-data-pointer device-select bank-select blink-select 7.18.1 Mode-set command Table 9. Bit [1] The possibility to disable the display allows implementation of blinking under external control. [2] Bit B is not applicable for the static LCD drive mode. 7.18.2 Load-data-pointer command Table 10 ...
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... NXP Semiconductors 7.18.3 Device-select command Table 11. Bit 7.18.4 Bank-select command Table 12. Bit [1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes. 7.18.5 Blink-select command Table 13. Bit [1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected. ...
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... NXP Semiconductors 8. Internal circuitry Fig 22. Device protection diagram PCF8576C Product data sheet Universal LCD driver for low multiplex rates V LCD V SS SDA, SCL CLK, OSC A2, SA0, SYNC V DD All information provided in this document is subject to legal disclaimers. Rev. 11 — 30 March 2012 ...
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... NXP Semiconductors 9. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (V LCD display artifacts. To avoid such artifacts, V Table 14. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD V LCD supply voltage ...
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... NXP Semiconductors 10. Static characteristics Table 15. Static characteristics LCD Symbol Parameter Supplies V supply voltage DD V LCD supply voltage LCD I supply current low-power mode supply DD(lp) current Logic V LOW-level input voltage IL V HIGH-level input voltage IH V LOW-level output voltage ...
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... NXP Semiconductors Table 15. Static characteristics …continued LCD Symbol Parameter LCD outputs V voltage on pin voltage on pin resistance on pin resistance on pin S S V for 1 [1] V ⁄ bias. LCD DD 3 [2] LCD outputs are open-circuit; inputs at V ...
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... NXP Semiconductors (μA) 40 normal mode f = 200 kHz clk 30 20 power-saving mode 10 f clk external clock; T LCD amb Fig 25 function 10.2 Typical LCD output characteristics 10 R O(max) (kΩ − LCD amb Fig 27 ...
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... NXP Semiconductors 11. Dynamic characteristics Table 16. Dynamic characteristics LCD Symbol Parameter Timing characteristics: driver timing waveforms (see f clock frequency clk t clock HIGH time clk(H) t clock LOW time clk(L) t SYNC propagation delay PD(SYNC_N) t SYNC LOW time SYNC_NL t driver propagation delay ...
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... NXP Semiconductors SYNC BP0 to BP3, and S0 to S39 Fig 29. Driver timing waveforms SDA SCL SDA Fig 30. I PCF8576C Product data sheet Universal LCD driver for low multiplex rates 1/f CLK t clk(H) CLK t PD(SYNC_N BUF LOW t HD;STA SU;STA 2 C-bus timing waveforms All information provided in this document is subject to legal disclaimers. Rev. 11 — ...
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... NXP Semiconductors 12. Application information 12.1 Cascaded operation In large display configurations PCF8576Cs can be recognized on the same 2 I C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable 2 I C-bus slave address (SA0). Table 17. Cluster 1 2 Cascaded PCF8576Cs are synchronized. They can share the backplane signals from one of the devices in the cascade ...
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... NXP Semiconductors V LCD V DD HOST MICRO- PROCESSOR/ MICRO- CONTROLLER V SS Fig 31. Cascaded PCF8576C configuration The SYNC line is provided to maintain the correct synchronization between all cascaded PCF8576Cs. This synchronization is guaranteed after the power-on reset. The only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments ...
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... NXP Semiconductors Excessive capacitive coupling between SCL or CLK and SYNC will cause erroneous synchronization. If this is a problem you can increase the capacitance of the SYNC line (e. external capacitor between SYNC and V can be countered by an external pull-up resistor. Fig 32. Synchronization of the cascade for the various PCF8576C drive modes ...
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... NXP Semiconductors SDA 1 SCL 2 SYNC 3 CLK OSC SA0 LCD BP0 13 BP2 14 BP1 15 BP3 S10 27 S11 28 S0 S10 S11 backplanes Fig 33. Single plane wiring of packaged PCF8576CT PCF8576C ...
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... NXP Semiconductors 13. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 0.27 mm 1.6 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors VSO56: plastic very small outline package; 56 leads pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 3.0 mm 3.3 0.25 0.1 2.8 0.012 0.12 inches 0.01 0.13 0.004 0.11 Notes 1. Plastic or metal protrusions of 0.3 mm (0.012 inch) maximum per side are not included. ...
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... NXP Semiconductors HTSSOP56: plastic thermal enhanced thin shrink small outline package; 56 leads; body width 6.1 mm; exposed die pad pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.05 0.27 mm 1.2 0.25 0.05 0.80 0.17 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...
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... NXP Semiconductors 14. Bare die outline Wire bond die; 56 bonding pads; 3.2 x 2. Dimensions (3) Unit max 0.610 nom mm 0.38 2.92 3.2 0.110 0.097 0.110 min 0.096 Note 1. Pad size 2. Passivation opening 3. Dimension not drawn to scale 4. Marking code: PC8576C-1 Outline version IEC PCF8576CU Fig 37 ...
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... NXP Semiconductors Bare die; 56 bumps; 3.2 x 2. Dimensions Unit max mm nom 0.398 0.0175 0.380 0.094 2.92 min Note 1. Dimension not drawn to scale 2. Marking code: PC8576C-2 Outline version IEC PCF8576CU/2 Fig 38. Bare die outline of PCF8576CU/2/F2 PCF8576C Product data sheet ...
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... NXP Semiconductors Table 18. All x/y coordinates represent the position of the center of each pad with respect to the center (x the chip. Symbol SDA SCL SYNC CLK V DD OSC SA0 LCD BP0 BP2 BP1 BP3 S10 S11 ...
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... NXP Semiconductors Table 18. All x/y coordinates represent the position of the center of each pad with respect to the center (x the chip. Symbol S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 Table 19. Symbol PCF8576C ...
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... NXP Semiconductors 15. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. 16. Packing information 16.1 Tray information ...
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... NXP Semiconductors Fig 40. Tray alignment Table 20. Symbol PCF8576C Product data sheet Universal LCD driver for low multiplex rates Tray dimensions Description pocket pitch; x direction pocket pitch; y direction pocket width; x direction pocket width; y direction tray width; x direction tray width ...
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... NXP Semiconductors 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 17.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 17.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors temperature MSL: Moisture Sensitivity Level Fig 41. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCF8576C Product data sheet Universal LCD driver for low multiplex rates ...
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... NXP Semiconductors 18. Abbreviations Table 23. Acronym CDM DC HBM LCD LSB MM MOS MSB MSL PCB POR RC RAM RMS SCL SDA SMD PCF8576C Product data sheet Universal LCD driver for low multiplex rates Abbreviations Description Charged-Device Model Direct Current Human Body Model ...
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... NXP Semiconductors 19. References [1] AN10170 — Design guidelines for COG modules with NXP monochrome LCD drivers [2] AN10365 — Surface mount reflow soldering description [3] AN10706 — Handling bare die [4] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [5] IEC 61340-5 — ...
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... NXP Semiconductors 20. Revision history Table 24. Revision history Document ID Release date PCF8576C v.11 20120330 • Modifications: Adjusted die size information • Added PCF8576C v.10 20100722 PCF8576C v.9 20090709 PCF8576C v.8 20041122 PCF8576C v.7 20011002 PCF8576C v.6 19980730 PCF8576C v.5 19971114 PCF8576C v.4 19970402 PCF8576C v.3 19970203 PCF8576C v.2 19961209 PCF8576C v.1 19950630 PCF8576C ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die ...
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... NXP Semiconductors 23. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Table 2. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2 Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .8 Table 4. Selection of possible display configurations . . . .9 Table 5. Biasing characteristics . . . . . . . . . . . . . . . . . . . 11 [1] Table 6. LCD frame frequencies Table 7. Blink frequencies . . . . . . . . . . . . . . . . . . . . . . .24 Table 8. Definition of PCF8576C commands . . . . . . . . .29 Table 9. Mode-set command bit description . . . . . . . . .29 Table 10. Load-data-pointer command bit description . . .29 Table 11 ...
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... NXP Semiconductors 24. Figures Fig 1. Block diagram of PCF8576C . . . . . . . . . . . . . . . . .3 Fig 2. Pin configuration for LQFP64 (PCF8576CHL/ Fig 3. Pin configuration for VSO56 (PCF8576CT/ Fig 4. Pin configuration for HTSSOP56 (PCF8576CTT/ Fig 5. Pin locations of PCF8576CU/F1 and PCF8576CU/2/ Fig 6. Example of displays suitable for PCF8576C . . . . .9 Fig 7. Typical system configuration . . . . . . . . . . . . . . . .10 Fig 8 ...
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... NXP Semiconductors 25. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 Functional description . . . . . . . . . . . . . . . . . . . 9 7.1 Power-On-Reset (POR 7.2 LCD bias generator . . . . . . . . . . . . . . . . . . . . 10 7.3 LCD voltage selector . . . . . . . . . . . . . . . . . . . 11 7.3.1 Electro-optical performance . . . . . . . . . . . . . . 12 7.4 LCD drive mode waveforms . . . . . . . . . . . . . . 14 7 ...