PCF8576CT/S480/1,1 NXP Semiconductors, PCF8576CT/S480/1,1 Datasheet - Page 39
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PCF8576CT/S480/1,1
Manufacturer Part Number
PCF8576CT/S480/1,1
Description
LCD Drivers Universal LCD Driver Low Multiplex Rates
Manufacturer
NXP Semiconductors
Datasheet
1.PCF8576CTS48011.pdf
(61 pages)
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NXP Semiconductors
PCF8576C
Product data sheet
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCF8576Cs. This synchronization is guaranteed after the power-on reset. The only time
that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in
adverse electrical environments; or by the defining a multiplex mode when PCF8576Cs
with differing SA0 levels are cascaded).
SYNC is organized as an input/output pin; the output selection being realized as an
open-drain driver with an internal pull-up resistor. A PCF8576C asserts the SYNC line and
monitors the SYNC line at all other times. If synchronization in the cascade is lost, it is
restored by the first PCF8576C to assert SYNC. The timing relationship between the
backplane waveforms and the SYNC signal for the various drive modes of the PCF8576C
are shown in
Fig 31. Cascaded PCF8576C configuration
V
V
V
LCD
DD
CONTROLLER
PROCESSOR/
SS
MICRO-
MICRO-
HOST
R
Figure
≤
2C
All information provided in this document is subject to legal disclaimers.
t
r
b
32.
Rev. 11 — 30 March 2012
SYNC
OSC
SDA
CLK
SCL
SYNC
SDA
SCL
CLK
OSC
A0
Universal LCD driver for low multiplex rates
A0
V
PCF8576C
DD
A1
PCF8576C
V
A1
DD
A2
A2 SAO V
V
LCD
SA0 V
V
LCD
SS
SS
40 segment drives
40 segment drives
4 backplanes
BP0 to BP3
BP0 to BP3
(open-circuit)
PCF8576C
© NXP B.V. 2012. All rights reserved.
LCD PANEL
(up to 2560
elements)
013aaa299
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