74AUP2G125GT-G NXP Semiconductors, 74AUP2G125GT-G Datasheet - Page 13

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74AUP2G125GT-G

Manufacturer Part Number
74AUP2G125GT-G
Description
Buffers & Line Drivers 1.8V DUAL BUS BUFFER LDRVR 3S
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74AUP2G125GT-G

Product Category
Buffers & Line Drivers
Rohs
yes
Number Of Input Lines
2
Number Of Output Lines
2
Polarity
Non-Inverting
Supply Voltage - Max
3.6 V
Supply Voltage - Min
0.8 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SOT-833-8
High Level Output Current
- 4 mA
Logic Family
AUP
Logic Type
CMOS
Low Level Output Current
4 mA
Minimum Operating Temperature
- 40 C
Number Of Channels Per Chip
2
Output Type
3-State
Propagation Delay Time
19 ns at 1.1 V to 1.3 V
Factory Pack Quantity
5000
Part # Aliases
74AUP2G125GT,115
NXP Semiconductors
Table 11.
[1]
74AUP2G125
Product data sheet
Supply voltage
V
0.8 V to 3.6 V
Fig 10. Test circuit for measuring switching times
CC
For measuring enable and disable times R
For measuring propagation delays, set-up and hold times, and pulse width, R
Test data is given in
C
R
V
Definitions for test circuit:
R
L
L
T
EXT
Test data
= Load resistance.
= Load capacitance including jig and probe capacitance.
= Termination resistance should be equal to the output impedance Z
= External voltage for measuring switching times.
Load
C
5 pF, 10 pF, 15 pF and 30 pF
L
Table
11.
L
All information provided in this document is subject to legal disclaimers.
G
= 5 k.
V I
Rev. 10 — 8 February 2013
R T
DUT
V
CC
R
5 k or 1 M
L
[1]
V O
L
C L
o
= 1 M.
001aac521
Low-power dual buffer/line driver; 3-state
of the pulse generator.
V
EXT
V
t
open
PLH
5 kΩ
R L
EXT
, t
PHL
74AUP2G125
t
GND
PZH
, t
PHZ
© NXP B.V. 2013. All rights reserved.
t
2  V
PZL
, t
CC
PLZ
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