74AUP2G125GT-G NXP Semiconductors, 74AUP2G125GT-G Datasheet - Page 3

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74AUP2G125GT-G

Manufacturer Part Number
74AUP2G125GT-G
Description
Buffers & Line Drivers 1.8V DUAL BUS BUFFER LDRVR 3S
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74AUP2G125GT-G

Product Category
Buffers & Line Drivers
Rohs
yes
Number Of Input Lines
2
Number Of Output Lines
2
Polarity
Non-Inverting
Supply Voltage - Max
3.6 V
Supply Voltage - Min
0.8 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SOT-833-8
High Level Output Current
- 4 mA
Logic Family
AUP
Logic Type
CMOS
Low Level Output Current
4 mA
Minimum Operating Temperature
- 40 C
Number Of Channels Per Chip
2
Output Type
3-State
Propagation Delay Time
19 ns at 1.1 V to 1.3 V
Factory Pack Quantity
5000
Part # Aliases
74AUP2G125GT,115
NXP Semiconductors
6. Pinning information
74AUP2G125
Product data sheet
Fig 3.
Fig 4.
Fig 6.
Logic diagram (one gate)
Pin configuration SOT765-1
Pin configuration SOT996-2
GND
1OE
1A
2Y
GND
1OE
1A
2Y
1
2
3
4
6.1 Pinning
1
2
3
4
Transparent top view
74AUP2G125
74AUP2G125
001aae973
8
7
6
5
001aaj471
All information provided in this document is subject to legal disclaimers.
V
2OE
1Y
2A
8
7
6
5
nOE
CC
nA
V
2OE
1Y
2A
CC
Rev. 10 — 8 February 2013
Fig 5.
Fig 7.
Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
Pin configuration SOT902-2
terminal 1
index area
mna227
Low-power dual buffer/line driver; 3-state
nY
2OE
1Y
2A
GND
1OE
1A
2Y
Transparent top view
1
2
3
74AUP2G125
Transparent top view
1
2
3
4
74AUP2G125
74AUP2G125
001aae974
8
7
6
5
V
2OE
1Y
2A
CC
© NXP B.V. 2013. All rights reserved.
7
6
5
001aae975
1OE
1A
2Y
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