MAX1366ECM-T Maxim Integrated, MAX1366ECM-T Datasheet - Page 22

• Manufacturer Part Number: MAX1366ECM-T
• Description: LED Display Drivers
• Manufacturer: Maxim Integrated

Specifications of MAX1366ECM-T

• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C

Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
At power-on, the serial interface, logic, LED drivers,
digital filter, modulator, and DAC circuits reset. The
registers return to their default values.
The SPI/QSPI/MICROWIRE serial interface consists of a
chip select (CS), a serial clock (SCLK), a data in (DIN),
a data out (DOUT), DAC chip select (CS_DAC), and an
EOC output. CS and CS_DAC enable access to regis-
ters in the MAX1366/MAX1368. CS allows a read and
write to all registers of the MAX1366/MAX1368 exclud-
ing the DAC register and CS_DAC enables a write to
the DAC register (see
of-conversion signal with a period of 200ms (f
4.9152MHz). The MAX1366/MAX1368 update the ADC
register when EOC goes high. Data is valid in the ADC
register when EOC returns low. The serial interface pro-
vides access to 13 on-chip registers, allowing control to
all the power modes and functional blocks.
the address and read/write accessibility of all the regis-
ters excluding the DAC register.
A logic-high on CS and CS_DAC tri-states DOUT and
causes the MAX1366/MAX1368 to ignore any signals
on SCLK and DIN. To clock data in or out of the internal
shift register, drive CS or CS_DAC low. SCLK synchro-
nizes the data transfer. The rising edge of SCLK clocks
DIN into the shift register, and the falling edge of SCLK
clocks DOUT out of the shift register. DIN and DOUT
are transferred MSB first (data is left justified).
6–10
for the 8- and 16-bit read/write operations.
All communication with the MAX1366/MAX1368, with
exception of the DAC register, begins with a command
byte on DIN, where the first logic one on DIN is recog-
nized as the START bit (MSB) for the command byte.
The following seven clock cycles load the command
into a shift register. These 7 bits specify which of the
22
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show the detailed serial-interface timing diagrams
Applications Information
Table
8). EOC provides an end-
Power-On Reset
Serial Interface
Table 6
Figures
CLK
lists
=
registers are accessed next, and whether a read or
write operation takes place. Transitions on the serial
clock after the command byte transfer, cause a write or
read from the device until the correct number of bits
have been transferred (8 or 16). Once this has
occurred, the MAX1366/MAX1368 wait for the next
command byte. CS must not go high between data
transfers. If CS is toggled before the end of a write or
read operation, the device mode may be unknown.
Clock in 32 zeros to clear the device state and reset the
interface so it is ready to receive a new command byte.
To write to the DAC register, pull CS_DAC low and
clock in 16 data bits. Data bits are clocked in MSB first
(see the DAC Operation section).
The MAX1366/MAX1368 contain 12 on-chip registers.
These registers configure the various functions of the
device and allow independent reading of the ADC
results and writing to the LED display.
address and size of each register. The first of these
registers is the status register. The 8-bit status register
contains the status flags for the ADC. The second reg-
ister is the 16-bit control register. This register sets the
LED display controls, range modes, power-down
modes, offset calibration, and the reset register func-
tion (CLR). The third register is the 16-bit overrange
register, which sets the overrange limit of the analog
input. The fourth register is the 16-bit underrange regis-
ter, which sets the underrange limit of the analog input.
Registers 5 through 7 contain the display data for the
individual segments of the LED. The eighth register
contains the custom offset value. The ninth register
contains the 16 MSBs of the ADC conversion result.
The 10th register contains the LED data. The 11th reg-
ister contains the peak analog input value. The last reg-
ister contains the lower 4 LSBs of the 20-bit ADC
conversion result.
On-Chip Registers (Excluding
DAC Register)
Table 6
lists the