MC10XS3412DHFK Freescale Semiconductor, MC10XS3412DHFK Datasheet - Page 50

• Manufacturer Part Number: MC10XS3412DHFK
• Description: Power Switch ICs - Power Distribution Eswitch Gen3 1012
• Manufacturer: Freescale Semiconductor

Specifications of MC10XS3412DHFK

• Rohs: yes
• Number Of Outputs: 4
• Operating Supply Voltage: 6 V to 20 V
• Supply Current (max): 20 mA
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: PQFN-24
• Minimum Operating Temperature: - 40 C

ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
technical data sheet. The addendum provides thermal performance
information that may be critical in the design and development of system
applications. All electrical, application and packaging information is
provided in the data sheet.
package independently heating with P
temperatures, T
reference temperature while only heat source 1 is heating with P
reference temperature while heat source 2 is heating with P
to R
one package to another in a standardized environment. This methodology is not meant to and will not predict the performance
of a package in an application-specific environment. Stated values were obtained by measurement and simulation according to
the standards listed below.
Standards
Table 25. Thermal Performance Comparison
50
10XS3412
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
Notes:
Introduction
This thermal addendum is provided as a supplement to the 10XS3412
Package and Thermal Considerations
This 10XS3412 is a dual die package. There are two heat sources in the
For m, n = 1, R
For m = 1, n = 2, R
The stated values are solely for a thermal performance comparison of
Resistance
1.
2.
3.
4.
5.
R
R
R
R
J21
Thermal



JCmn
JA mn
JB mn
JA mn
Per JEDEC JESD51-2 at natural convection, still air
condition.
2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
and R
(5)
(1)(2)
(2)(3)
(1)(4)
J22
T
T
J1
J1
J2
JA11
and T
, respectively.
m = 1,
1 = Power Chip, 2 = Logic Chip
26.04
13.21
46.42
n = 1
0.67
=
JA12
is the thermal resistance from Junction 1 to the
J2
R
R
, and a thermal resistance matrix with R
JA11
JA21
is the thermal resistance from Junction 1 to the
m = 1, n = 2
m = 2, n = 1
R
R
JA12
JA22
18.18
37.03
6.40
0.95
1
and P
.
2
P
P
. This results in two junction
1
2
[C/W]
m = 2,
35.49
23.94
53.82
n = 2
0.00
2
. This applies
1
.
JAmn
Figure 15. Detail of Copper Traces Under Device with
.
Note For package dimensions, refer to
98ARL10596D.
Analog Integrated Circuit Device Data
24-PIN PQFN (12 x 12)
Thermal Vias
10XS3412
98ARL10596D
24-PIN
PQFN
Freescale Semiconductor
0.2mm
0.5mm dia.
0.2mm