74AHCT2G00DP-G NXP Semiconductors, 74AHCT2G00DP-G Datasheet

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74AHCT2G00DP-G

Manufacturer Part Number
74AHCT2G00DP-G
Description
Logic Gates DUAL 2-INPUT NAND GATE
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74AHCT2G00DP-G

Product Category
Logic Gates
Rohs
yes
Product
NAND
Logic Family
AHCT
Number Of Gates
2
Number Of Lines (input / Output)
2 / 1
High Level Output Current
- 8 mA
Low Level Output Current
8 mA
Propagation Delay Time
3.6 ns
Supply Voltage - Max
5.5 V
Supply Voltage - Min
4.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SOT-505
Minimum Operating Temperature
- 40 C
Number Of Input Lines
2
Number Of Output Lines
1
Factory Pack Quantity
3000
Part # Aliases
74AHCT2G00DP,125
1. General description
2. Features and benefits
3. Ordering information
Table 1.
Type number
74AHC2G00DP
74AHCT2G00DP
74AHC2G00DC
74AHCT2G00DC
74AHC2G00GD
74AHCT2G00GD
Ordering information
Package
Temperature range Name
40 C to +125 C
40 C to +125 C
40 C to +125 C
The 74AHC2G00; 74AHCT2G00 are high-speed Si-gate CMOS devices. They provide
two 2-input NAND gates.
The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V.
The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V.
74AHC2G00; 74AHCT2G00
Dual 2-input NAND gate
Rev. 3 — 27 March 2013
Symmetrical output impedance
High noise immunity
ESD protection:
Low power dissipation
Balanced propagation delays
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
TSSOP8
VSSOP8
XSON8
Description
plastic thin shrink small outline package; 8 leads; body
width 3 mm; lead length 0.5 mm
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
plastic extremely thin small outline package; no leads;
8 terminals; body 3  2  0.5 mm
Product data sheet
Version
SOT505-2
SOT765-1
SOT996-2

Related parts for 74AHCT2G00DP-G

74AHCT2G00DP-G Summary of contents

Page 1

... Specified from 40 C to +85 C and from 40 C to +125 C  3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 40 C to +125 C 74AHC2G00DP 74AHCT2G00DP 40 C to +125 C 74AHC2G00DC 74AHCT2G00DC 40 C to +125 C 74AHC2G00GD 74AHCT2G00GD Description TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm ...

Page 2

... NXP Semiconductors 4. Marking Table 2. Marking Type number 74AHC2G00DP 74AHCT2G00DP 74AHC2G00DC 74AHCT2G00DC 74AHC2G00GD 74AHCT2G00GD [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 001aah748 Fig 1. Logic symbol Fig 3. Logic diagram (one gate) 74AHC_AHCT2G00 Product data sheet 74AHC2G00 ...

Page 3

... NXP Semiconductors 6. Pinning information 6.1 Pinning 74AHC2G00 74AHCT2G00 GND 4 001aaj388 Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) 6.2 Pin description Table 3. Pin description Symbol Pin 1A 1B GND 4 1Y Functional description [1] Table 4. Function table ...

Page 4

... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I I input clamping current IK I output clamping current OK I output current O I supply current ...

Page 5

... NXP Semiconductors Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V LOW-level input voltage HIGH-level output voltage = 50  50  50  4.0 mA 8.0 mA ...

Page 6

... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics GND = 0 V; for test circuit see Figure Symbol Parameter Conditions 74AHC2G00 t propagation nA nY; see pd delay power per buffer; PD dissipation pF; f ...

Page 7

... NXP Semiconductors 12. Waveforms Measurement points are given in Logic levels: V and Fig 6. The input (nA and nB) to output (nY) propagation delays. Table 9. Measurement points Type Input V M 74AHC2G00 0.5V CC 74AHCT2G00 1.5 V 74AHC_AHCT2G00 Product data sheet 74AHC2G00; 74AHCT2G00 nA, nB input M GND t PHL output ...

Page 8

... NXP Semiconductors negative Test data is given in Table Definitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistance Test selection switch. Fig 7. Test circuit for measuring switching times Table 10. Test data ...

Page 9

... NXP Semiconductors 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.00 0.75 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...

Page 10

... NXP Semiconductors VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0. 0.12 0.00 0.60 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

Page 11

... NXP Semiconductors XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 0.5 mm terminal 1 index area Dimensions (mm are the original dimensions) (1) Unit max 0.05 0.35 2.1 mm nom 0.5 min 0.00 0.15 1.9 Outline version IEC SOT996-2 Fig 10. Package outline SOT996-2 (XSON8) 74AHC_AHCT2G00 Product data sheet 74AHC2G00 ...

Page 12

... NXP Semiconductors 14. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date 74AHC_AHCT2G00 v.3 20130327 • ...

Page 13

... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 14

... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

Page 15

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 13 Package outline ...

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