74AHCT2G00DP-G NXP Semiconductors, 74AHCT2G00DP-G Datasheet - Page 9
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74AHCT2G00DP-G
Manufacturer Part Number
74AHCT2G00DP-G
Description
Logic Gates DUAL 2-INPUT NAND GATE
Manufacturer
NXP Semiconductors
Datasheet
1.74AHC2G00DC-G.pdf
(15 pages)
Specifications of 74AHCT2G00DP-G
Product Category
Logic Gates
Rohs
yes
Product
NAND
Logic Family
AHCT
Number Of Gates
2
Number Of Lines (input / Output)
2 / 1
High Level Output Current
- 8 mA
Low Level Output Current
8 mA
Propagation Delay Time
3.6 ns
Supply Voltage - Max
5.5 V
Supply Voltage - Min
4.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SOT-505
Minimum Operating Temperature
- 40 C
Number Of Input Lines
2
Number Of Output Lines
1
Factory Pack Quantity
3000
Part # Aliases
74AHCT2G00DP,125
NXP Semiconductors
13. Package outline
Fig 8.
74AHC_AHCT2G00
Product data sheet
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
UNIT
mm
Package outline SOT505-2 (TSSOP8)
VERSION
OUTLINE
SOT505-2
max.
1.1
A
0.15
0.00
A 1
8
1
0.95
0.75
A 2
y
pin 1 index
IEC
e
Z
0.25
A 3
D
0.38
0.22
b p
b p
All information provided in this document is subject to legal disclaimers.
0
5
0.18
0.08
4
JEDEC
c
- - -
w
REFERENCES
D
3.1
2.9
M
(1)
Rev. 3 — 27 March 2013
E
3.1
2.9
(1)
c
JEITA
scale
74AHC2G00; 74AHCT2G00
0.65
2.5
e
A
H E
4.1
3.9
A 2
A 1
0.5
L
H E
E
5 mm
0.47
0.33
detail X
L p
0.2
v
L
L p
PROJECTION
EUROPEAN
0.13
w
A
(A 3 )
Dual 2-input NAND gate
0.1
y
X
v
θ
M
0.70
0.35
Z
© NXP B.V. 2013. All rights reserved.
A
(1)
ISSUE DATE
02-01-16
8°
0°
θ
SOT505-2
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