MCIMX6Q6AVT10AC Freescale Semiconductor, MCIMX6Q6AVT10AC Datasheet - Page 75
MCIMX6Q6AVT10AC
Manufacturer Part Number
MCIMX6Q6AVT10AC
Description
Processors - Application Specialized i.MX6Q
Manufacturer
Freescale Semiconductor
Type
Multimedia Applicationsr
Datasheet
1.MCIMX6Q6AVT10AC.pdf
(166 pages)
Specifications of MCIMX6Q6AVT10AC
Rohs
yes
Core
ARM Cortex A9
Processor Series
i.MX6
Data Bus Width
32 bit
Maximum Clock Frequency
1 GHz
Data Ram Size
16 KB
Operating Supply Voltage
1.05 V to 1.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
FCBGA
Interface Type
I2C, I2S, UART, USB
Memory Type
L1/L2 Cache, ROM, SRAM
Minimum Operating Temperature
- 40 C
Number Of Timers
2
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4.11.2.1 ECSPI Master Mode Timing
Figure 41
characteristics.
Freescale Semiconductor
CS10
ECSPI slow includes:
ECSPI3/DISP0_DAT2
ECSPI fast includes:
See specific I/O AC parameters
ECSPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CS8
CS9
ECSPI1/DISP0_DAT22, ECSPI1/KEY_COL1, ECSPI1/CSI0_DAT6, ECSPI2/EIM_OE, ECSPI2/ ECSPI2/CSI0_DAT10,
ECSPI1/EIM_D17, ECSPI4/EIM_D22, ECSPI5/SD2_DAT0, ECSPI5/SD1_DAT0
ID
ECSPIx_RDY_B
ECSPIx_SS_B
ECSPIx_MOSI
ECSPIx_MISO
ECSPIx_SCLK
ECSPIx_SCLK Cycle Time–Read
ECSPIx_SCLK Cycle Time–Write
ECSPIx_SCLK High or Low Time–Read
ECSPIx_SCLK High or Low Time–Write
ECSPIx_SCLK Rise or Fall
ECSPIx_SSx pulse width
ECSPIx_SSx Lead Time (CS setup time)
ECSPIx_SSx Lag Time (CS hold time)
ECSPIx_MOSI Propagation Delay (C
ECSPIx_MISO Setup Time
ECSPIx_MISO Hold Time
ECSPIx_RDY to ECSPIx_SSx Time
• Slow group
• Fast group
• Slow group
• Fast group
• Slow group
• Fast group
depicts the timing of ECSPI in master mode and
CS10
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2
CS8
2
2
2
1
1
1
Parameter
CS1
Table 52. ECSPI Master Mode Timing Parameters
Section 4.7, “I/O AC Parameters.”
CS7
Figure 41. ECSPI Master Mode Timing Diagram
CS9
3
CS3
4
CS3
LOAD
= 20 pF)
CS2
t
Symbol
RISE/FALL
t
PDmosi
t
Table 52
t
t
t
Hmiso
CSLH
t
t
Smiso
SDRY
t
SCS
HCS
t
SW
clk
CS2
Half ECSPIx_SCLK period - 4
Half ECSPIx_SCLK period - 2
lists the ECSPI master mode timing
Half ECSPIx_SCLK period
CS6
21.5
Min
55
40
15
26
20
16
—
-1
7
0
5
CS4
Electrical Characteristics
CS5
Max Unit
—
—
—
—
—
—
—
—
—
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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