MCIMX6Q6AVT10AC Freescale Semiconductor, MCIMX6Q6AVT10AC Datasheet - Page 95

• Manufacturer Part Number: MCIMX6Q6AVT10AC
• Description: Processors - Application Specialized i.MX6Q
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6Q6AVT10AC

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 16 KB
• Operating Supply Voltage: 1.05 V to 1.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FCBGA
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

1
2
3
4
4.11.10 Image Processing Unit (IPU) Module Parameters
The purpose of the IPU is to provide comprehensive support for the flow of data from an image sensor
and/or to a display device. This support covers all aspects of these activities:
Freescale Semiconductor
A device must internally provide a hold time of at least 300 ns for I2Cx_SDA signal in order to bridge the undefined region of
the falling edge of I2Cx_SCL.
The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2Cx_SCL signal.
A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7)
of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2Cx_SCL signal.
If such a device does stretch the LOW period of the I2Cx_SCL signal, it must output the next data bit to the I2Cx_SDA line
max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification)
before the I2Cx_SCL line is released.
C
IC10
IC11
IC12
IC9
b
ID
•
•
•
= total capacitance of one bus line in pF.
Connectivity to relevant devices
Related image processing and manipulation: sensor image signal processing, display processing,
image conversions, and other related functions.
Synchronization and control capabilities, such as avoidance of tearing artifacts.
Bus free time between a STOP and START condition
Rise time of both I2Cx_SDA and I2Cx_SCL signals
Fall time of both I2Cx_SDA and I2Cx_SCL signals
Capacitive load for each bus line (C
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2
Table 66. I
Parameter
2
C Module Timing Parameters (continued)
b
—
)
cameras, displays, graphics accelerators, and TV encoders.
Min
4.7
—
—
—
Standard Mode
1000
Max
300
400
—
Electrical Characteristics
20 + 0.1C
20 + 0.1C
Fast Mode
Min
1.3
—
b
b
4
4
Max
300
300
400
—
Unit
µ
ns
ns
pF
s
95