P5010NXN1TNB Freescale Semiconductor, P5010NXN1TNB Datasheet - Page 139

• Manufacturer Part Number: P5010NXN1TNB
• Description: Processors - Application Specialized P5010 Ext Tmp NoEnc 1800/1333 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5010NXN1TNB

• Rohs: yes

3.1.4
The clock frequency of each the e5500 core 0–1 complex is determined by the binary value of the RCW field CCn_PLL_SEL.
This table describes the supported ratios for each core complex 0-1, where each individual core complex can select a frequency
from the table.
For this table, if CC2 PLL is used by core0, then CC2 PLL must be operated at a lower frequency than the CC1 PLL, and its
maximum allowed frequency is 80% of the maximum rated frequency of the core at nominal voltage. Similarly, if CC1 PLL is
used by core1, then CC1 PLL must be operated at a lower frequency than the CC2 PLL, and its maximum allowed frequency
is 80% of the maximum rated frequency of the core at nominal voltage.
3.1.5
The dual DDR memory controller complexes can be synchronous with or asynchronous to the platform, depending on
configuration. Both DDR controllers operate at the same frequency configuration. For P5010, only the DDR-1 controller is
available.
Table 103
(asynchronous mode) or from the platform clock (synchronous mode).
In asynchronous DDR mode, the DDR data rate to SYSCLK ratios supported are listed in
by the binary value of the RCW Configuration field MEM_PLL_RAT[10:14].
The RCW Configuration field MEM_PLL_CFG[8:9] must be set to MEM_PLL_CFG[8:9] = 0b01 if the applied DDR PLL
reference clock frequency is greater than the cutoff frequency listed in
synchronous DDR clock ratios respectively, else set MEM_PLL_CFG[8:9]=b’00.
Freescale Semiconductor
describes the clock ratio between the DDR memory controller PLLs and the externally supplied SYSCLK input
Binary Value of Cn_PLL_SEL
e5500 Core Complex PLL Select
DDR Controller PLL Ratios
The RCW Configuration field DDR_SYNC (bit 184) must be set to b’0 for asynchronous
mode, and b’1 for synchronous mode.
The RCW Configuration field DDR_RATE (bit 232) must be set to b’0 for asynchronous
mode, and b’1 for synchronous mode.
All Others
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
0000
0001
0100
0101
Table 102. Core Complex [0,1] PLL Select
e5500 Core Complex 0 Clock
CC1 PLL /1
CC1 PLL /2
CC2 PLL /1
NOTE
Reserved
Reserved
Table 103
and
Table 104
e5500 Core Complex 1 Clock
Table
Hardware Design Considerations
CC1 PLL /1
CC2 PLL /1
CC2 PLL /2
for asynchronous and
Reserved
Reserved
103. This ratio is determined
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