P5010NXN1TNB Freescale Semiconductor, P5010NXN1TNB Datasheet - Page 59

• Manufacturer Part Number: P5010NXN1TNB
• Description: Processors - Application Specialized P5010 Ext Tmp NoEnc 1800/1333 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5010NXN1TNB

• Rohs: yes

This figure shows the undershoot and overshoot voltages at the interfaces of the chip.
The core and platform voltages must always be provided at nominal 1.0 V or 1.1 V. See
core voltage conditions. Voltage to the processor interface I/Os is provided through separate sets of supply pins and must be
provided at the voltages shown in
CV
specifications. The DDR SDRAM interface uses differential receivers referenced by the externally supplied MV
(nominally set to GV
operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded.
Freescale Semiconductor
DD
, BV
DD
V
Note:
t
For I2C, t
For DDR GV
For eSPI CV
For eLBC BV
For SerDes XV
For dTSEC LV
For JTAG OV
. F or SerDes SV
, OV
CLOCK
IH
Figure 8. Overshoot/Undershoot Voltage for BV
DD
Nominal C/X/S/B/G/L/OV
DD
refers to the clock period associated with the respective interface:
, and LV
CLOCK
/2) as is appropriate for the SSTL_1.5 electrical signaling standard. The DDR DQS receivers cannot be
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
DD
DD
DD
DD
DD
, t
DD
DD
, t
, t
, t
refers to SYSCLK.
DD
C/X/S/B/G/L/OV
, t
CLOCK
CLOCK
CLOCK
CLOCK
, t
, t
V
CLOCK
CLOCK
CLOCK
-based receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type
IL
Table
C/X/S/B/G/L/OV
refers to SPI_CLK.
refers to Dn_MCK.
refers to TCK.
refers to LCLK.
refers to EC_GTX_CLK125.
refers to SD_REF_CLK.
refers to SD_REF_CLK.
3. The input voltage threshold scales with respect to the associated I/O supply voltage.
GND – 0.7 V
GND – 0.3V
DD
DD
+ 20%
+ 5%
GND
DD
DD
/GV
Not to Exceed 10%
DD
of t
/LV
CLOCK
DD
Table 3
/OV
DD
/SV
for the actual recommended
Electrical Characteristics
DD
/XV
DD
REF
n signal
59