MCIMX6U6AVM08ABR Freescale Semiconductor, MCIMX6U6AVM08ABR Datasheet - Page 12
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MCIMX6U6AVM08ABR
Manufacturer Part Number
MCIMX6U6AVM08ABR
Description
Processors - Application Specialized i.MX6 DualLite
Manufacturer
Freescale Semiconductor
Type
Multimedia Applicationsr
Datasheet
1.MCIMX6S6AVM08ABR.pdf
(174 pages)
Specifications of MCIMX6U6AVM08ABR
Rohs
yes
Core
ARM Cortex A9
Processor Series
i.MX6
Data Bus Width
32 bit
Maximum Clock Frequency
800 MHz
Data Ram Size
16 KB
Operating Supply Voltage
1.175 V to 1.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
MAPBGA-624
Interface Type
Parallel
Memory Type
L1/L2 Cache, ROM, SRAM
Minimum Operating Temperature
- 40 C
Number Of Timers
2
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Modules List
12
Block Mnemonic
FlexCAN-1
FlexCAN-2
uSDHC-1
uSDHC-2
uSDHC-3
uSDHC-4
i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1
Card / Secure Digital Host
Flexible Controller Area
Enhanced Multi-Media
SD/MMC and SDXC
Block Name
Controller
Network
Table 2. i.MX 6Solo/6DualLite Modules List (continued)
Subsystem
Connectivity
Connectivity
Peripherals
Peripherals
i.MX 6Solo/6DualLite specific SoC characteristics:
All four MMC/SD/SDIO controller IPs are identical and
are based on the uSDHC IP. They are:
All four ports support:
However, the SoC level integration and I/O muxing logic
restrict the functionality to the following:
The CAN protocol was primarily, but not only, designed
to be used as a vehicle serial data bus, meeting the
specific requirements of this field: real-time processing,
reliable operation in the Electromagnetic interference
(EMI) environment of a vehicle, cost-effectiveness and
required bandwidth. The FlexCAN module is a full
implementation of the CAN protocol specification,
Version 2.0 B, which supports both standard and
extended message frames.
• Fully compliant with MMC command/response sets
• Fully compliant with SD command/response sets and
• Fully compliant with SDIO command/response sets
• 1-bit or 4-bit transfer mode specifications for SD and
• 1-bit, 4-bit, or 8-bit transfer mode specifications for
• Instances #1 and #2 are primarily intended to serve
• Instances #3 and #4 are primarily intended to serve
• All ports can work with 1.8 V and 3.3 V cards. There
and Physical Layer as defined in the Multimedia Card
System Specification, v4.2/4.3/4.4 including
high-capacity (size > 2 GB) cards HC MMC.
Physical Layer as defined in the SD Memory Card
Specifications, v3.0 including high-capacity SDHC
cards up to 32 GB.
and interrupt/read-wait mode as defined in the SDIO
Card Specification, Part E1, v3.0
SDIO cards up to UHS-I SDR104 mode (104 MB/s
max)
MMC cards up to 52 MHz in both SDR and DDR
modes (104 MB/s max)
as external slots or interfaces to on-board SDIO
devices. These ports are equipped with “Card
detection” and “Write Protection” pads and do not
support hardware reset.
interfaces to embedded MMC memory or interfaces
to on-board SDIO devices. These ports do not have
“Card detection” and “Write Protection” pads and do
support hardware reset.
are two completely independent I/O power domains
for Ports #1 and #2 in four bit configuration (SD
interface). Port #3 is placed in his own independent
power domain and port #4 shares power domain with
some other interfaces.
Brief Description
Freescale Semiconductor
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