MCIMX508CZK8B Freescale Semiconductor, MCIMX508CZK8B Datasheet - Page 67

• Manufacturer Part Number: MCIMX508CZK8B
• Description: Processors - Application Specialized CODEX REV 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX508CZK8B

• Core: ARM Cortex A8
• Processor Series: i.MX50

4.8
This section includes descriptions of the electrical specifications of DRAM MC module which interfaces
external DDR2, LPDDR1, and LPDDR2 memory devices.
Freescale Semiconductor
1
2
3
4
5
6
7
8
WE34 EIM_RW invalid to EIM_CSx invalid
WE35 EIM_CSx valid to EIM_OE valid
WE36 EIM_OE invalid to EIM_CSx invalid
WE37 EIM_CSx valid to EIM_EBx valid
WE38 EIM_EBx invalid to EIM_CSx invalid
WE39 EIM_CSx valid to EIM_LBA valid
WE40 EIM_LBA invalid to EIM_CSx invalid
WE41 EIM_CSx valid to Output Data valid
WE42 Output Data invalid to EIM_CSx
WE43 Input Data valid to EIM_CSx invalid
WE44 EIM_CSx invalid to Input Data invalid
WE45 EIM_CSx valid to EIM_EBx valid
WE46 EIM_EBx invalid to EIM_CSx invalid
WE47 EIM_DTACK valid to EIM_CSx
WE48 EIM_CSx invalid to EIM_DTACK
Parameters WE4–WE21 value, see in the
EIM_CSx Assertion. This bit field determines when EIM_CSx signal is asserted during read/write cycles.
EIM_CSx Negation. This bit field determines when EIM_CSx signal is negated during read/write cycles.
EIM_EBx Assertion. This bit field determines when EIM_EBx signal is asserted during read cycles.
EIM_EBx Negation. This bit field determines when EIM_EBx signal is negated during read cycles.
Output maximum delay from internal driving the FFs to chip outputs. The maximum delay between all memory controls
(EIM_ADDR, EIM_CSx, EIM_OE, EIM_RW, EIM_EBx, and EIM_LBA).
Maximum delay from chip input data to internal FFs. The maximum delay between all data input pins.
DTACK maximum delay from chip input data to internal FF.
ID
(Read access)
(Read access)
(ADVL is asserted)
invalid
(Write access)
(Write access)
invalid
invalid
DRAM Timing Parameters
Table 43. EIM Asynchronous Timing Parameters Table Relative Chip Select (continued)
Parameter
i.MX50 Applications Processors for Consumer Products, Rev. 4
Table
WE7 – WE9 + (WEN – CSN)
WE10 – WE6 + (OEA – CSA)
WE7 – WE11 + (OEN – CSN)
WE12 – WE6 + (RBEA – CSA)
WE7 – WE13 + (RBEN – CSN)
WE14 – WE6 + (ADV – CSA)
WE7 – WE15 – CSN
WE16 – WE6 – WCSA
WE17 – WE7 – CSN
WE7 – WE13 + (WBEN – CSN)
WE12 – WE6 + (WBEA – CSA)
43.
Synchronous Measured
MAXCO + MAXDTI
Determination by
MAXCO + MAXDI
Parameters
0
0
1
MAXCO
MAXCO
MAXDI
XDTI
Min
—
—
—
—
—
—
—
—
—
—
—
0
0
6
8
+ MA
6
7
+
–3 + (WBEN – CSN)
Electrical Characteristics
3 + (RBEA
3 – (RBEN
3 + (WBEA – CSA)
3 + (ADVA – CSA)
3 – (OEN – CSN)
3 + (OEA – CSA)
3 – (WEN_CSN)
3 – WCSA
3 – CSN
3 – CSN
Max
—
—
—
—
4
5
– CSN)
– CSA)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
67