IS42S16400F-6TL ISSI, Integrated Silicon Solution Inc, IS42S16400F-6TL Datasheet - Page 13

• Manufacturer Part Number: IS42S16400F-6TL
• Description: IC SDRAM 64MBIT 166MHZ 54TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S16400F-6TL

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 130mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 166 MHz
• Access Time: 6 ns, 5.4 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 130 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 706-1075; IS42S16400F-6TL

IS42S16400F
IC42S16400F
AC ELECTRICAL CHARACTERISTICS
Notes:
1. When power is first applied, memory operation should be started 200 µs after V
2. measured with t
3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between V
4. Access time is measured at 1.4V with the load shown in the figure below.
5. The time t
6. If clock rising time is longer than 1ns, tr/
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
03/19/08
Symbol Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
ck3
ck2
ac3
ac2
chi
cl
oh3
oh2
lz
hz3
hz2
Ds
Dh
as
ah
cks
ckh
cka
cs
ch
rc
ras
rp
rcD
rrD
Dpl
wr
Dal
t
ref
note that the power-on sequence must be executed before starting memory operation.
(max.).
when the output is in the high impedance state.
or
Clock Cycle Time
Access Time From CLK
CLK HIGH Level Width
CLK LOW Level Width
Output Data Hold Time
Output LOW Impedance Time
Output HIGH Impedance Time
Input Data Setup Time
Input Data Hold Time
Address Setup Time
Address Hold Time
CKE Setup Time
CKE Hold Time
CKE to CLK Recovery Delay Time
Command Setup Time (CS, RAS, CAS, WE, DQM)
Command Hold Time (CS, RAS, CAS, WE, DQM)
Command Period (REF to REF / ACT to ACT)
Command Period (ACT to PRE)
Command Period (PRE to ACT)
Active Command To Read / Write Command Delay Time
Command Period (ACT [0] to ACT[1])
Input Data To Precharge
Command Delay time
Input Data To Active / Refresh
Command Delay time (During Auto-Precharge)
Transition Time
Refresh Cycle Time (4096)
hz
(max.) is defined as the time required for the output voltage to transition by ± 200 mV from V
t
= 1 ns.
(6)
(4,6)
(5)
2
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2
- 0.5ns should be added to the parameter.
(1,2,3)
2CLK+t
2CLK+t
1CLK+3
2CLK
2CLK
Min.
7.5
2.5
2.5
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
60
42
18
18
12
—
—
—
—
—
6
2
2
0
1
rp
rp
-6
100,000
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10
64
5
6
5
6
DD
and V
2CLK+t
2CLK+t
1CLK+3
2CLK
2CLK
Min.
7.5
2.5
2.5
2.7
1.5
0.8
1.5
0.8
1.5
0.8
2.0
—
—
—
—
63
42
20
20
14
—
7
3
0
1
1
DDq
-7
rp
rp
100,000
reach their stipulated voltages. Also
Max.
5.4
5.4
10
64
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6
6
2CLK+t
2CLK+t
1CLK+3
2CLK
2CLK
Min.
0.8
1.5
0.8
0.8
7.5
2.5
2.5
1.5
0.8
1.5
1.5
oh
55
42
15
15
10
—
—
—
—
—
5
2
2
0
1
(min.) or V
-5
rp
rp
ih
(min.) and V
100,000
Max.
10
64
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
6
5
6
1
ol
(max.)
Units
il
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13