IS61LV25616AL-12TI ISSI, IS61LV25616AL-12TI Datasheet
IS61LV25616AL-12TI
Specifications of IS61LV25616AL-12TI
Related parts for IS61LV25616AL-12TI
IS61LV25616AL-12TI Summary of contents
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... Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61LV25616AL is packaged in the JEDEC standard 44-pin 400-mil SOJ, 44-pin TSOP Type II, 44-pin LQFP and 48-pin Mini BGA (8mm x 10mm). A0-A17 DECODER VDD GND I/O DATA CIRCUIT CE OE CONTROL WE CIRCUIT UB LB 1-800-379-4774 DECEMBER 2011 IS61LV25616AL is a high-speed, 4,194,304-bit ISSI 's high-performance CMOS technol- 256K x 16 MEMORY ARRAY COLUMN I/O 1 ...
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... IS61LV25616AL TRUTH TABLE Mode WE CE Not Selected X Output Disabled H X Read Write PIN CONFIGURATIONS 44-Pin TSOP (Type II) and SOJ I/O0 7 I/O1 8 I/O2 9 I/O3 10 VDD 11 GND 12 I/O4 13 I/O5 14 I/ ...
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... IS61LV25616AL PIN CONFIGURATIONS 44-Pin LQFP I/O0 3 I/O1 4 I/O2 5 I/O3 TOP VIEW 6 VDD 7 GND 8 I/O4 9 I/O5 10 I/ PIN DESCRIPTIONS A0-A17 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input OE Output Enable Input Write Enable Input WE Lower-byte Control (I/O0-I/O7 Upper-byte Control (I/O8-I/O15 Connection V Power DD GND Ground Integrated Silicon Solution, Inc. — ...
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... IS61LV25616AL ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Terminal Voltage with Respect to GND term t Storage Temperature stg P Power Dissipation t Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE Range Ambient Temperature Commercial 0°C to +70°C Industrial – ...
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... IS61LV25616AL POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions I V Dynamic Operating Supply Current I out I TTL Standby Current (TTL Inputs ≥ TTL Standby Current (TTL Inputs ≥ CMOS Standby Current (CMOS Inputs) CE ≥ V In Note address and data inputs are cycling at the maximum frequency means no input lines change. ...
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... IS61LV25616AL READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Read Cycle Time rc t Address Access Time aa t Output Hold Time oHa t CE Access Time ace t OE Access Time Doe High-Z Output (2) Hzoe t ( Low-Z Output Lzoe High-Z Output Hzce Low-Z Output (2) Lzce t LB, UB Access Time ba t (2) LB High-Z Output Hzb t LB Low-Z Output (2) Lzb t Power Up Time Pu t Power Down Time ...
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... IS61LV25616AL AC WAVEFORMS READ CYCLE NO. 1 (1,2) (Address Controlled) ( ADDRESS D OUT PREVIOUS DATA VALID READ CYCLE NO. 2 (1,3) ADDRESS LZCE LB HIGH-Z D OUT V DD Supply Current Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB Address is valid prior to or coincident with CE LOW transition. Integrated Silicon Solution, Inc. — www.issi.com — ...
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... IS61LV25616AL READ CYCLE NO. 2 (1,3) ADDRESS LZCE LB LZB HIGH-Z D OUT V DD Supply Current Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB Address is valid prior to or coincident with CE LOW transition. WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Write Cycle Time Write End sce t Address Setup Time to Write End aw t Address Hold from Write End ...
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... IS61LV25616AL AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled HIGH or LOW) ADDRESS UB DATA UNDEFINED OUT D IN Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state WRITE = (CE) (LB) = (UB) (WE). WRITE CYCLE NO. 2 (WE Controlled HIGH During Write Cycle) ADDRESS OE CE LOW ...
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... IS61LV25616AL AC WAVEFORMS WRITE CYCLE NO. 3 (WE Controlled LOW During Write Cycle) ADDRESS OE LOW CE LOW UB DATA UNDEFINED OUT D IN WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) ADDRESS OE CE LOW WE UB HZWE D OUT DATA UNDEFINED D IN Notes: 1. The internal Write time is defined by the overlap Low, UB and/ Low, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write ...
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... IS61LV25616AL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter V V for Data Retention Data Retention Current Dr t Data Retention Setup Time See Data Retention Waveform sDr t Recovery Time rDr Note 1: Typical values are measured 3.0V DATA RETENTION WAVEFORM V DD 1.65V 1. GND Integrated Silicon Solution, Inc. — www.issi.com — Rev. F 12/15/2011 (LL) Test Condition Options See Data Retention Waveform V = 2.0V, CE ≥ ...
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... Speed (ns) Order Part No. 10 IS61LV25616AL-10TI IS61LV25616AL-10TLI IS61LV25616AL-10KI IS61LV25616AL-10KLI IS61LV25616AL-10LQI IS61LV25616AL-10LQLI IS61LV25616AL-10BI IS61LV25616AL-10BLI 12 IS61LV25616AL-12TI 12 Package TSOP (Type II) TSOP (Type II), Lead-free 400-mil SOJ TSOP (Type II) Package TSOP (Type II) TSOP (Type II), Lead-free 400-mil SOJ 400-mil SOJ, Lead-free LQFP LQFP, Lead-free Mini BGA (8mm x 10mm) Mini BGA (8mm x 10mm), Lead-free TSOP (Type II) Integrated Silicon Solution, Inc. — ...
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... IS61LV25616AL Integrated Silicon Solution, Inc. — www.issi.com — Rev. F 12/15/2011 1-800-379-4774 13 ...
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... IS61LV25616AL 14 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 12/15/2011 ...
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... IS61LV25616AL Integrated Silicon Solution, Inc. — www.issi.com — Rev. F 12/15/2011 1-800-379-4774 15 ...
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... IS61LV25616AL 16 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 12/15/2011 ...