C8051F347-GMR Silicon Labs, C8051F347-GMR Datasheet - Page 172
C8051F347-GMR
Manufacturer Part Number
C8051F347-GMR
Description
8-bit Microcontrollers - MCU 25 MIPS 32KB 10 ADC
Manufacturer
Silicon Labs
Datasheet
1.C8051F349-GMR.pdf
(276 pages)
Specifications of C8051F347-GMR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
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C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
16.8. Interrupts
The read-only USB0 interrupt flags are located in the USB registers shown in USB Register
Definition 16.11 through USB Register Definition 16.13. The associated interrupt enable bits are located in
the USB registers shown in USB Register Definition 16.14 through USB Register Definition 16.16. A USB0
interrupt is generated when any of the USB interrupt flags is set to ‘1’. The USB0 interrupt is enabled via
the EIE1 SFR (see
Important Note: Reading a USB interrupt flag register resets all flags in that register to ‘0’.
172
Bits7-0:
Bits7-3:
Bits2-0:
Bit7
Bit7
R
R
-
USB Register Definition 16.10. FRAMEH: USB0 Frame Number High
USB Register Definition 16.9. FRAMEL: USB0 Frame Number Low
Frame Number Low
This register contains bits7-0 of the last received frame number.
Unused. Read = 0. Write = don’t care.
Frame Number High Byte
This register contains bits10-8 of the last received frame number.
Bit6
Bit6
R
R
-
Section “9.3. Interrupt Handler” on page 88
Bit5
Bit5
R
R
-
Frame Number Low
Bit4
Bit4
R
R
-
Rev. 1.3
Bit3
Bit3
R
R
-
Bit2
Bit2
R
R
Frame Number High
).
Bit1
Bit1
R
R
Bit0
Bit0
R
R
USB Address:
USB Address:
00000000
00000000
Reset Value
Reset Value
0x0C
0x0D
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