W25Q80BVSSIG Winbond Electronics, W25Q80BVSSIG Datasheet - Page 14
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W25Q80BVSSIG
Manufacturer Part Number
W25Q80BVSSIG
Description
IC FLASH 8MBIT 8SOIC
Manufacturer
Winbond Electronics
Datasheet
1.W25Q80BVSSIG.pdf
(75 pages)
Specifications of W25Q80BVSSIG
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
8M (1M x 8)
Speed
104MHz
Interface
SPI Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4816329
T1015683
T1015683
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
W25Q80BVSSIG
Manufacturer:
Winbond
Quantity:
2 100
Company:
Part Number:
W25Q80BVSSIG
Manufacturer:
WINBOND
Quantity:
192
Part Number:
W25Q80BVSSIG
Manufacturer:
WINBOND/华邦
Quantity:
20 000
9.1.10
The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI
operation. When the QE bit is set to a 0 state (factory default), the /WP pin and /HOLD are enabled.
When the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled, and /WP and /HOLD functions are
disabled.
WARNING: If the /WP or /HOLD pins are tied directly to the power supply or ground during
standard SPI or Dual SPI operation, the QE bit should never be set to a 1.
Quad Enable (QE)
SECURITY REGISTER LOCK BITS
SECURITY REGISTER LOCK BITS
STATUS REGISTER PROTECT 0
STATUS REGISTER PROTECT 0
STATUS REGISTER PROTECT 1
STATUS REGISTER PROTECT 1
ERASE/WRITE IN PROGRESS
ERASE/WRITE IN PROGRESS
TOP/BOTTOM PROTECT
TOP/BOTTOM PROTECT
COMPLEMENT PROTECT
COMPLEMENT PROTECT
BLOCK PROTECT BITS
BLOCK PROTECT BITS
WRITE ENABLE LATCH
WRITE ENABLE LATCH
SECTOR PROTECT
SECTOR PROTECT
SUSPEND STATUS
SUSPEND STATUS
(non-volatile OTP)
(non-volatile OTP)
QUAD ENABLE
QUAD ENABLE
(non-volatile)
(non-volatile)
(non-volatile)
(non-volatile)
(non-volatile)
(non-volatile)
(non-volatile)
(non-volatile)
(non-volatile)
(non-volatile)
(non-volatile)
(non-volatile)
(non-volatile)
(non-volatile)
RESERVED
RESERVED
Figure 3a. Status Register-1
Figure 3b. Status Register-2
SRP0
SRP0
S7
S7
S15
S15
SUS
SUS
- 14 -
SEC
SEC
S6
S6
CMP
CMP
S14
S14
S5
S5
TB
TB
S13
S13
LB3
LB3
BP2
BP2
S4
S4
S12
S12
LB2
LB2
BP1
BP1
S3
S3
S11
S11
LB1
LB1
BP0
BP0
S2
S2
S10
S10
(R)
(R)
WEL BUSY
WEL BUSY
S1
S1
S9
S9
QE
QE
SRP1
SRP1
S0
S0
W25Q80BV
S8
S8