W25Q16BVSSIG Winbond Electronics, W25Q16BVSSIG Datasheet - Page 23

• Manufacturer Part Number: W25Q16BVSSIG
• Description: IC SPI FLASH 16MBIT 8SOIC
• Manufacturer: Winbond Electronics

Specifications of W25Q16BVSSIG

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 16M (2M x 8)
• Speed: 104MHz
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

W25Q16BV
11.2.8 Write Status Register (01h)
The Write Status Register instruction allows the Status Register to be written. A Write Enable instruction
must previously have been executed for the device to accept the Write Status Register Instruction (Status
Register bit WEL must equal 1). Once write enabled, the instruction is entered by driving /CS low,
sending the instruction code “01h”, and then writing the status register data byte as illustrated in figure 7.
The Status Register bits are shown in figure 3 and described earlier in this datasheet.
Only non-volatile Status Register bits SRP0, SEC, TB, BP2, BP1, BP0 (bits 7, 5, 4, 3, 2 of Status
Register-1) and QE, SRP1(bits 9 and 8 of Status Register-2) can be written to. All other Status Register
bit locations are read-only and will not be affected by the Write Status Register instruction.
The /CS pin must be driven high after the eighth or sixteenth bit of data that is clocked in. If this is not
done the Write Status Register instruction will not be executed. If /CS is driven high after the eighth clock
(compatible with the 25X series) the QE and SRP1 bits will be cleared to 0. After /CS is driven high, the
self-timed Write Status Register cycle will commence for a time duration of t
(See AC Characteristics).
W
While the Write Status Register cycle is in progress, the Read Status Register instruction may still be
accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle
and a 0 when the cycle is finished and ready to accept other instructions again. After the Write Register
cycle has finished the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.
The Write Status Register instruction allows the Block Protect bits (SEC, TB, BP2, BP1 and BP0) to be
set for protecting all, a portion, or none of the memory from erase and program instructions. Protected
areas become read-only (see Status Register Memory Protection table and description). The Write Status
Register instruction also allows the Status Register Protect bits (SRP0, SRP1) to be set. Those bits are
used in conjunction with the Write Protect (/WP) pin, Lock out or OTP features to disable writes to the
status register. Please refer to 11.1.6 for detailed descriptions regarding Status Register protection
methods. Factory default for all status Register bits are 0.
Figure 7. Write Status Register Instruction Sequence Diagram
Publication Release Date: July 08, 2010
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Revision F