S9S08SG8E2VTJR Freescale Semiconductor, S9S08SG8E2VTJR Datasheet - Page 41

• Manufacturer Part Number: S9S08SG8E2VTJR
• Description: 8-bit Microcontrollers - MCU 9S08 UC W/ 8K 0.25UM SGF
• Manufacturer: Freescale Semiconductor

Specifications of S9S08SG8E2VTJR

• Rohs: yes
• Core: HCS08
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 512 B
• On-chip Adc: Yes
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TSSOP-20
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 12
• Interface Type: I2C, SCI, SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

1
2
Table 3-1
conditions. The selected mode is entered following the execution of a STOP instruction.
3.6.1
Stop3 mode is entered by executing a STOP instruction under the conditions as shown in
states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained.
Stop3 can be exited by asserting RESET, or by an interrupt from one of the following sources: the real-time
counter (RTC), LVD system, ACMP, ADC, SCI or any pin interrupts.
If stop3 is exited by means of the RESET pin, then the MCU is reset and operation will resume after taking
the reset vector. Exit by means of one of the internal interrupt sources results in the MCU taking the
appropriate interrupt vector.
3.6.1.1
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. For configuring the LVD system for interrupt or reset, refer to
Detect (LVD)
time the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode.
For the ADC to operate in stop mode, the LVD must be enabled when entering stop3.
For the ACMP to operate in stop mode with compare to internal bandgap option, the LVD must be enabled
when entering stop3.
3.6.1.2
Entry into the active background mode from run mode is enabled if ENBDM in BDCSCR is set. This
register is described in
STOP instruction, the system clocks to the background debug logic remain active when the MCU enters
stop mode. Because of this, background debug communication remains possible. In addition, the voltage
regulator does not enter its low-power standby state but maintains full internal regulation.
Freescale Semiconductor
STOPE
ENBDM is located in the BDCSCR, which is only accessible through BDC commands, see
Control Register
When in Stop3 mode with BDM enabled, The S
0
1
1
1
1
shows all of the control bits that affect stop mode selection and the mode selected under various
ENBDM
Stop3 Mode
LVD Enabled in Stop3 Mode
Active BDM Enabled in Stop3 Mode
1
0
0
0
x
System”. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the
(BDCSCR)”.
1
Both bits must be 1
LVDE
Either bit a 0
Either bit a 0
Chapter 17, “Development
x
x
LVDSE
Table 3-1. Stop Mode Selection
PPDC
MC9S08SG32 Data Sheet, Rev. 8
x
x
x
0
1
IDD
will be near R
Stop modes disabled; illegal opcode reset if STOP instruction executed
Stop3 with BDM enabled
Stop3 with voltage regulator active
Stop3
Stop2
Support.” If ENBDM is set when the CPU executes a
IDD
levels because internal clocks are enabled.
2
Stop Mode
Section 17.4.1.1, “BDC Status and
Section 5.6, “Low-Voltage
Chapter 3 Modes of Operation
Table
3-1. The
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