CY7C1339G-133AXC Cypress Semiconductor Corp, CY7C1339G-133AXC Datasheet - Page 11

• Manufacturer Part Number: CY7C1339G-133AXC
• Description: IC SRAM 4MBIT 133MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1339G-133AXC

• Memory Size: 4M (128K x 32)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 4 ns
• Maximum Clock Frequency: 133 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 225 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2112; CY7C1339G-133AXC

Switching Characteristics
Over the Operating Range
Document Number: 38-05520 Rev. *I
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Set-up Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Notes
POWER
CYC
CH
CL
CO
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
AS
ADS
ADVS
WES
DS
CES
AH
ADH
ADVH
WEH
DH
CEH
13. This part has a voltage regulator internally; t
14. t
15. At any given voltage and temperature, t
16. This parameter is sampled and not 100% tested.
17. Timing reference level is 1.5 V when V
18. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Parameter
can be initiated.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve high Z prior to low Z under the same system conditions.
CHZ
, t
CLZ
,t
OELZ
, and t
V
Clock cycle time
Clock HIGH
Clock LOW
Data output valid after CLK rise
Data output hold after CLK rise
Clock to low Z
Clock to high Z
OE LOW to output valid
OE LOW to output low Z
OE HIGH to output high Z
Address set-up before CLK rise
ADSC, ADSP set-up before CLK rise
ADV set-up before CLK rise
GW, BWE, BW
Data input set-up before CLK rise
Chip enable set-up before CLK rise
Address hold after CLK rise
ADSP, ADSC hold after CLK rise
ADV hold after CLK rise
GW, BWE, BW
Data input hold after CLK rise
Chip enable hold after CLK rise
DD
OEHZ
(Typical) to the first access
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
[13, 14, 15, 16, 17, 18]
[14, 15, 16]
[14, 15, 16]
X
X
Description
DDQ
OEHZ
set-up before CLK rise
hold after CLK rise
POWER
= 3.3 V and is 1.25 V when V
is less than t
[14, 15, 16]
is the time that the power needs to be supplied above V
[14, 15, 16]
OELZ
[13]
and t
CHZ
is less than t
DDQ
Min
4.0
1.7
1.7
1.0
1.2
1.2
1.2
1.2
1.2
1.2
0.3
0.3
0.3
0.3
0.3
0.3
= 2.5 V.
1
–
0
–
–
0
–
–250
CLZ
Max
2.6
2.6
2.6
2.6
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
to eliminate bus contention between SRAMs when sharing the same
Min
5.0
2.0
2.0
1.0
1.2
1.2
1.2
1.2
1.2
1.2
0.5
0.5
0.5
0.5
0.5
0.5
1
–
0
–
–
0
–
–200
Max
DD
2.8
2.8
2.8
2.8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(minimum) initially before a read or write operation
Min
1.5
0.5
0.5
6.0
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
–
–
1
0
–
0
–
–166
Max
3.5
3.5
3.5
3.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Min
7.5
3.0
3.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
–
0
–
–
0
–
CY7C1339G
–133
Max
4.0
4.0
4.0
4.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Page 11 of 21
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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