CY7C1338G-100AXC Cypress Semiconductor Corp, CY7C1338G-100AXC Datasheet - Page 11

• Manufacturer Part Number: CY7C1338G-100AXC
• Description: IC SRAM 4MBIT 100MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1338G-100AXC

• Memory Size: 4M (128K x 32)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 8 ns
• Maximum Clock Frequency: 100 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 205 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Density: 4Mb
• Access Time (max): 8ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 205mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 32b
• Number Of Words: 128K
• Memory Configuration: 128K X 32
• Clock Frequency: 100MHz
• Supply Voltage Range: 3.135V To 3.6V
• Memory Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Switching Characteristics
Over the Operating Range
Document Number: 38-05521 Rev. *F
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Setup Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Notes:
POWER
CYC
CH
CL
CDV
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
AS
ADS
ADVS
WES
DS
CES
AH
ADH
WEH
ADVH
DH
CEH
12. This part has a voltage regulator internally; t
13. t
14. At any given voltage and temperature, t
15. This parameter is sampled and not 100% tested.
16. Timing reference level is 1.5 V when V
17. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
can be initiated.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve high Z prior to low Z under the same system conditions.
CHZ
Parameter
, t
CLZ
,t
OELZ
, and t
OEHZ
V
Clock cycle time
Clock HIGH
Clock LOW
Data output valid after CLK rise
Data output hold after CLK rise
Clock to low Z
Clock to high Z
OE LOW to output valid
OE LOW to output low Z
OE HIGH to output high Z
Address set-up before CLK rise
ADSP, ADSC set-up before CLK rise
ADV set-up before CLK rise
GW, BWE, BW
Data input set-up before CLK rise
Chip enable set-up
Address hold after CLK rise
ADSP, ADSC hold after CLK rise
GW, BWE, BW
ADV hold after CLK rise
Data input hold after CLK rise
Chip enable hold after CLK rise
DD
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
(Typical) to the first access
[12, 13, 14, 15, 16, 17]
DDQ
OEHZ
[13, 14, 15]
[13, 14, 15]
X
X
POWER
= 3.3 V and is 1.25 V when V
is less than t
set-up before CLK rise
hold after CLK rise
is the time that the power needs to be supplied above V
Description
[13, 14, 15]
[13, 14, 15]
OELZ
and t
[12]
CHZ
is less than t
DDQ
= 2.5 V.
CLZ
to eliminate bus contention between SRAMs when sharing the same
DD
Min
2.5
7.5
2.5
2.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
–
0
–
–
0
–
(minimum) initially before a read or write operation
–133
Max
6.5
3.5
3.5
3.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Min
4.0
4.0
2.0
2.0
2.0
2.0
2.0
1.5
2.0
0.5
0.5
0.5
0.5
0.5
0.5
10
1
–
0
–
–
0
–
–100
CY7C1338G
Max
8.0
3.5
3.5
3.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Page 11 of 21
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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