CY7C1338G-100AXC Cypress Semiconductor Corp, CY7C1338G-100AXC Datasheet - Page 6

• Manufacturer Part Number: CY7C1338G-100AXC
• Description: IC SRAM 4MBIT 100MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1338G-100AXC

• Memory Size: 4M (128K x 32)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 8 ns
• Maximum Clock Frequency: 100 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 205 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Density: 4Mb
• Access Time (max): 8ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 205mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 32b
• Number Of Words: 128K
• Memory Configuration: 128K X 32
• Clock Frequency: 100MHz
• Supply Voltage Range: 3.135V To 3.6V
• Memory Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

available at the data outputs a maximum to t
ADSP is ignored if CE
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE
and (2) ADSP is asserted LOW. The addresses presented are
loaded into the address register and the burst inputs (GW, BWE,
and BW
inputs are asserted active (see Write Cycle Descriptions table for
appropriate states that indicate a write) on the next clock rise, the
appropriate data will be latched and written into the device. Byte
writes are allowed. During byte writes, BW
BWB controls DQ
All I/Os are tri-stated during a byte write.Since this is a common
I/O device, the asynchronous OE input signal must be
deasserted and the I/Os must be tri-stated prior to the presen-
tation of data to DQs. As a safety precaution, the data lines are
tri-stated once a write cycle is detected, regardless of the state
of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BW
indicate a write access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the memory
core. The information presented to DQ
specified address location. Byte writes are allowed. During byte
writes, BW
DQ
is detected, even a byte write. Since this is a common I/O device,
the asynchronous OE input signal must be deasserted and the
I/Os must be tri-stated prior to the presentation of data to DQs.
As a safety precaution, the data lines are tri-stated once a write
cycle is detected, regardless of the state of OE.
ZZ Mode Electrical Characteristics
Document Number: 38-05521 Rev. *F
I
t
t
t
t
DDZZ
ZZS
ZZREC
ZZI
RZZI
C
Parameter
, and BW
[A:D]
A
)are ignored during this first clock cycle. If the write
controls DQ
D
controls DQ
B
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ inactive to exit sleep current
. BWC controls DQ
1
is HIGH.
A
, BW
D
1
. All I/Os are tri-stated when a write
, CE
1
, CE
B
2
Description
controls DQ
, CE
2
, and CE
C
[A:D]
, and BW
3
are all asserted active,
will be written into the
A
CDV
controls DQ
3
B
are all asserted
D
, BW
after clock rise.
controls DQ
C
controls
A
[A:D]
and
D
.
)
ZZ > V
ZZ > V
ZZ < 0.2 V
This parameter is sampled
This parameter is sampled
Burst Sequences
The CY7C1338G provides an on-chip two-bit wraparound burst
counter inside the SRAM. The burst counter is fed by A[1:0], and
can follow either a linear or interleaved burst order. The burst
order is determined by the state of the MODE input. A LOW on
MODE will select a linear burst sequence. A HIGH on MODE will
select an interleaved burst order. Leaving MODE unconnected
will cause the device to default to a interleaved burst sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CEs,
ADSP, and ADSC must remain inactive for the duration of t
after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or V
Linear Burst Address Table (MODE = GND)
Test Conditions
DD
DD
Address
Address
A1, A0
– 0.2 V
A
– 0.2 V
First
First
1
00
01
10
00
01
10
11
11
, A
0
Address
Address
Second
Second
A1, A0
A
1
01
00
10
01
10
11
00
11
, A
0
2t
Min
CYC
–
–
–
0
DD
Address
Address
A1, A0
A
)
Third
Third
1
10
00
01
10
11
00
01
11
, A
2t
2t
Max
0
40
CYC
CYC
–
–
CY7C1338G
Address
Address
Fourth
Fourth
A1, A0
A
Page 6 of 21
Unit
mA
1
ns
ns
ns
ns
10
01
00
11
00
01
10
11
, A
0
ZZREC
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