CY7C1363C-133AXC Cypress Semiconductor Corp, CY7C1363C-133AXC Datasheet - Page 11

IC SRAM 9MBIT 133MHZ 100LQFP

CY7C1363C-133AXC

Manufacturer Part Number
CY7C1363C-133AXC
Description
IC SRAM 9MBIT 133MHZ 100LQFP
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1363C-133AXC

Memory Size
9M (512K x 18)
Format - Memory
RAM
Memory Type
SRAM - Synchronous
Speed
133MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Memory Configuration
512K X 18 / 256K X 36
Clock Frequency
133MHz
Access Time
6.5ns
Supply Voltage Range
3.135V To 3.6V
Memory Case Style
TQFP
No. Of Pins
100
Density
9Mb
Access Time (max)
6.5ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
133MHz
Operating Supply Voltage (typ)
3.3V
Address Bus
19b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
250mA
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Word Size
18b
Number Of Words
512K
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
428-2131
CY7C1363C-133AXC

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C1363C-133AXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7C1363C-133AXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
ZZ Mode Electrical Characteristics
Truth Table
The Truth Table for CY7C1361C and CY7C1363C follows.
Document Number: 38-05541 Rev. *J
I
t
t
t
t
Deselected cycle, power-down
Deselected cycle, power-down
Deselected cycle, power-down
Deselected cycle, power-down
Deselected cycle, power-down
Sleep mode, power-down
Read cycle, begin burst
Read cycle, begin burst
Write cycle, begin burst
Read cycle, begin burst
Read cycle, begin burst
Read cycle, continue burst
Read cycle, continue burst
Read cycle, continue burst
Read cycle, continue burst
Write cycle, continue burst
Write cycle, continue burst
Read cycle, suspend burst
Read cycle, suspend burst
Read cycle, suspend burst
Read cycle, suspend burst
Write cycle, suspend burst
Write cycle, suspend burst
Notes
DDZZ
ZZS
ZZREC
ZZI
RZZI
5. X=”Don't Care.” H = Logic HIGH, L = Logic LOW.
6. WRITE = L when any one or more byte write enable signals and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
7. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
8. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
9. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
Parameter
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Cycle Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
Description
Address
External
External
External
External
External
Current
Current
Current
Current
Current
Current
Used
None
None
None
None
None
None
Next
Next
Next
Next
Next
Next
CE
H
X
X
X
X
H
H
X
H
X
X
H
H
X
H
L
L
L
L
L
L
L
L
1
CE
ZZ > V
ZZ > V
ZZ < 0.2 V
This parameter is sampled
This parameter is sampled
X
X
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
2
CE
X
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
DD
DD
[5, 6, 7, 8, 9]
3
– 0.2 V
– 0.2 V
ZZ
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Test Conditions
ADSP
X
H
H
X
H
H
H
H
H
X
X
H
H
H
X
X
H
X
L
L
L
L
X
ADSC
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
Commercial/
L
L
L
L
L
L
Automotive
Industrial
ADV WRITE OE CLK
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
L
L
L
L
L
L
X
. Writes may occur only on subsequent clocks
CY7C1361C/CY7C1363C
H
H
H
H
H
H
X
X
X
X
X
X
X
X
H
H
H
H
2t
L
L
L
L
L
Min
CYC
0
H
H
H
H
H
H
X
X
X
X
X
X
L
X
L
L
L
X
X
L
L
X
X
2t
2t
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
Max
50
60
X
CYC
CYC
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Page 11 of 34
DQ
Q
D
Q
Q
Q
D
D
Q
Q
D
D
Unit
mA
mA
ns
ns
ns
ns
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