CY7C1363C-133AXC Cypress Semiconductor Corp, CY7C1363C-133AXC Datasheet - Page 16

IC SRAM 9MBIT 133MHZ 100LQFP

CY7C1363C-133AXC

Manufacturer Part Number
CY7C1363C-133AXC
Description
IC SRAM 9MBIT 133MHZ 100LQFP
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1363C-133AXC

Memory Size
9M (512K x 18)
Format - Memory
RAM
Memory Type
SRAM - Synchronous
Speed
133MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Memory Configuration
512K X 18 / 256K X 36
Clock Frequency
133MHz
Access Time
6.5ns
Supply Voltage Range
3.135V To 3.6V
Memory Case Style
TQFP
No. Of Pins
100
Density
9Mb
Access Time (max)
6.5ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
133MHz
Operating Supply Voltage (typ)
3.3V
Address Bus
19b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
250mA
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Word Size
18b
Number Of Words
512K
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
428-2131
CY7C1363C-133AXC

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C1363C-133AXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7C1363C-133AXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
TAP AC Switching Characteristics
Over the Operating Range
Document Number: 38-05541 Rev. *J
Clock
t
t
t
t
Output Times
t
t
Set-up Times
t
t
t
Hold Times
t
t
t
Notes
Parameter
TCYC
TF
TH
TL
TDOV
TDOX
TMSS
TDIS
CS
TMSH
TDIH
CH
12. t
13. Test conditions are specified using the load in TAP AC test conditions. t
CS
and t
CH
refer to the setup and hold time requirements of latching data from the boundary scan register.
TCK clock cycle time
TCK clock frequency
TCK clock HIGH time
TCK clock LOW time
TCK clock LOW to TDO valid
TCK clock LOW to TDO invalid
TMS setup to TCK clock rise
TDI setup to TCK clock rise
Capture setup to TCK rise
TMS hold after TCK clock rise
TDI hold after clock rise
Capture hold after clock rise
[12, 13]
Parameter
R
/t
F
= 1 ns.
CY7C1361C/CY7C1363C
Min
50
20
20
0
5
5
5
5
5
5
Max
20
10
Page 16 of 34
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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