CY7C1460AV25-200BZC Cypress Semiconductor Corp, CY7C1460AV25-200BZC Datasheet - Page 19

• Manufacturer Part Number: CY7C1460AV25-200BZC
• Description: IC SRAM 36MBIT 200MHZ 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1460AV25-200BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 36M (1M x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Document #: 38-05354 Rev. *D
Switching Characteristics
t
Clock
t
F
t
t
Output Times
t
t
t
t
t
t
t
Set-up Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Notes:
17. This part has a voltage regulator internally; t
18. t
19. At any given voltage and temperature, t
20. This parameter is sampled and not 100% tested.
21. Timing reference is 1.25V when V
22. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Power
CYC
CH
CL
CO
EOV
DOH
CHZ
CLZ
EOHZ
EOLZ
AS
DS
CENS
WES
ALS
CES
AH
DH
CENH
WEH
ALH
CEH
MAX
Parameter
initiated.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
CHZ
[17]
, t
CLZ
, t
EOLZ
, and t
V
Clock Cycle Time
Maximum Operating Frequency
Clock HIGH
Clock LOW
Data Output Valid After CLK Rise
OE LOW to Output Valid
Data Output Hold After CLK Rise
Clock to High-Z
Clock to Low-Z
OE HIGH to Output High-Z
OE LOW to Output Low-Z
Address Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
CEN Set-up Before CLK Rise
WE, BW
ADV/LD Set-up Before CLK Rise
Chip Select Set-up
Address Hold After CLK Rise
Data Input Hold After CLK Rise
CEN Hold After CLK Rise
WE, BW
ADV/LD Hold after CLK Rise
Chip Select Hold After CLK Rise
CC
EOHZ
(typical) to the first access read or write
x
x
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
Set-up Before CLK Rise
Hold After CLK Rise
DDQ
[18, 19, 20]
Description
[18, 19, 20]
= 2.5V and 0.9V when V
EOHZ
Over the Operating Range
power
is less than t
is the time power needs to be supplied above V
[18, 19, 20]
[18, 19, 20]
EOLZ
DDQ
and t
= 1.8V.
CHZ
is less than t
[21, 22]
Min.
4.0
1.5
1.5
1.0
1.2
1.2
1.2
1.2
0.3
0.3
0.3
1.0
1.2
1.2
0.3
0.3
0.3
1
0
–250
CLZ
Max.
to eliminate bus contention between SRAMs when sharing the same
250
2.6
2.6
2.6
2.6
DD
minimum initially, before a Read or Write operation can be
Min.
5.0
2.0
2.0
1.5
1.3
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
1
0
–200
Max.
200
3.2
3.0
3.0
3.0
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
Min.
6.0
2.4
2.4
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
0
–167
Max.
167
3.4
3.4
3.4
3.4
Page 19 of 27
Unit
MHz
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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