CAT34C02YI-G ON Semiconductor, CAT34C02YI-G Datasheet - Page 7

• Manufacturer Part Number: CAT34C02YI-G
• Description: IC EEPROM 2KBIT 400KHZ 8TSSOP
• Manufacturer: ON Semiconductor

Specifications of CAT34C02YI-G

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2K (256 x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TSSOP
• Organization: 256 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.7 V
• Maximum Operating Current: 1 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 1.8 V , 2.5 V , 3.3 V , 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 34C02YI-G

Read Operations
Immediate Address Read
points to the data byte immediately following the last byte
accessed by a previous operation. If that ‘previous’ byte was
the last byte in memory, then the address counter will point
to the 1
with a Slave address containing a ‘1’ in the R/W bit position
(Figure 10), it will acknowledge (ACK) in the 9
and will then transmit data being pointed at by the internal
address counter. The Master can stop further transmission by
issuing a NoACK, followed by a STOP condition.
Selective Read
different from the one stored in the internal address counter.
In standby mode, the CAT34C02 internal address counter
When, following a START, the CAT34C02 is presented
The Read operation can also be started at an address
BUS ACTIVITY:
st
memory byte, etc.
SDA LINE
MASTER
BUS ACTIVITY:
SCL
SDA
SDA LINE
MASTER
ADDRESS
SLAVE
S
S
A
R
T
T
BUS ACTIVITY:
A
C
K
ADDRESS
SDA LINE
SLAVE
MASTER
Figure 10. Immediate Address Read Timing
DATA n
DATA OUT
Figure 12. Sequential Read Timing
Figure 11. Selective Read Timing
8th Bit
th
8
clock cycle,
S
A
C
K
R
S
T
A
T
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ADDRESS (n)
A
C
K
ADDRESS
BYTE
SLAVE
DATA n+1
7
The address counter can be initialized by performing a
‘dummy’ Write operation (Figure 11). Here the START is
followed by the Slave address (with the R/W bit set to ‘0’)
and the desired byte address. Instead of following up with
data, the Master then issues a 2
‘Immediate Address Read’ sequence, as described earlier.
Sequential Read
by the CAT34C02, then the device will continue
transmitting as long as each data byte is acknowledged by
the Master (Figure 12). If the end of memory is reached
during sequential Read, then the address counter will
‘wrap−around’ to the beginning of memory, etc. Sequential
Read works with either ‘Immediate Address Read’ or
‘Selective Read’, the only difference being the starting byte
address.
If the Master acknowledges the 1
C
A
K
C
A
K
NO ACK
S
A
R
S
T
T
A
C
K
9
ADDRESS
DATA
SLAVE
DATA n+2
O
N
A
C
K
P
C
O
A
K
S
T
P
A
C
K
DATA n
STOP
nd
START, followed by the
DATA n+x
st
data byte transmitted
N
O
A
C
K
O
P
S
P
T
N
O
C
A
K
S
O
P
T
P